Lines Matching refs:RECEIVE_STATUS

491 #define RECEIVE_STATUS		BIT5  macro
1197 usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); in mgsl_isr_receive_status()
1548 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS); in mgsl_isr_misc()
1549 usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS); in mgsl_isr_misc()
1835 usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS | in shutdown()
4815 usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); in usc_set_sdlc_mode()
5055 usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA | in usc_set_sdlc_mode()
5432 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS); in usc_process_rxoverrun_sync()
5433 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS); in usc_process_rxoverrun_sync()
5446 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS ); in usc_process_rxoverrun_sync()
5447 usc_EnableInterrupts( info, RECEIVE_STATUS ); in usc_process_rxoverrun_sync()
5487 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS ); in usc_stop_receiver()
5488 usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS ); in usc_stop_receiver()
5535 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS ); in usc_start_receiver()
5536 usc_EnableInterrupts( info, RECEIVE_STATUS ); in usc_start_receiver()
5550 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS); in usc_start_receiver()
5963 usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); in usc_set_async_mode()
6043 RECEIVE_DATA + RECEIVE_STATUS ); in usc_set_async_mode()
6046 RECEIVE_DATA + RECEIVE_STATUS ); in usc_set_async_mode()