Lines Matching refs:BIT3
493 #define TRANSMIT_STATUS BIT3
510 #define RXSTATUS_CRC_ERROR BIT3
511 #define RXSTATUS_FRAMING_ERROR BIT3
550 #define TXSTATUS_CRC_SENT BIT3
570 #define MISCSTATUS_RCC_UNDERRUN BIT3
596 #define SICR_RCC_UNDERFLOW BIT3
630 #define TXSTATUS_CRC_SENT BIT3
1452 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); in mgsl_isr_receive_data()
1610 if ( status & BIT3 ) { in mgsl_isr_receive_dma()
5059 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); in usc_set_sdlc_mode()
5452 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); in usc_process_rxoverrun_sync()
5541 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); in usc_start_receiver()
5647 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 ); in usc_start_transmitter()
5924 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5981 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
6128 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1)) in usc_loopback_frame()
7332 if ( status & (BIT8 | BIT3 | BIT1) ) { in mgsl_dma_test()