118 	reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);  in sirfsoc_uart_tx_empty()
130 		if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &  in sirfsoc_uart_get_mctrl()
158 		current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;  in sirfsoc_uart_set_mctrl()
182 				rd_regl(port, ureg->sirfsoc_int_en_reg) &  in sirfsoc_uart_stop_tx()
191 				rd_regl(port, ureg->sirfsoc_int_en_reg) &  in sirfsoc_uart_stop_tx()
222 				rd_regl(port, ureg->sirfsoc_int_en_reg)&  in sirfsoc_uart_tx_with_dma()
238 			rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|  in sirfsoc_uart_tx_with_dma()
249 				rd_regl(port, ureg->sirfsoc_int_en_reg)|  in sirfsoc_uart_tx_with_dma()
259 			rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&  in sirfsoc_uart_tx_with_dma()
298 					rd_regl(port, ureg->sirfsoc_int_en_reg)|  in sirfsoc_uart_start_tx()
316 				rd_regl(port, ureg->sirfsoc_int_en_reg) &  in sirfsoc_uart_stop_rx()
327 				rd_regl(port, ureg->sirfsoc_int_en_reg)&  in sirfsoc_uart_stop_rx()
346 				rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);  in sirfsoc_uart_disable_ms()
349 					rd_regl(port, ureg->sirfsoc_int_en_reg)&  in sirfsoc_uart_disable_ms()
381 				rd_regl(port, ureg->sirfsoc_afc_ctrl) |  in sirfsoc_uart_enable_ms()
385 					rd_regl(port, ureg->sirfsoc_int_en_reg)  in sirfsoc_uart_enable_ms()
399 		unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);  in sirfsoc_uart_break_ctl()
419 	while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &  in sirfsoc_uart_pio_rx_chars()
421 		ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |  in sirfsoc_uart_pio_rx_chars()
446 		!(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &  in sirfsoc_uart_pio_tx_chars()
540 			rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |  in sirfsoc_rx_tmo_process_tl()
549 				rd_regl(port, ureg->sirfsoc_int_en_reg) &  in sirfsoc_rx_tmo_process_tl()
560 				rd_regl(port, ureg->sirfsoc_int_en_reg) |  in sirfsoc_rx_tmo_process_tl()
583 			rd_regl(port, ureg->sirfsoc_int_en_reg) &  in sirfsoc_uart_handle_rx_tmo()
603 				rd_regl(port, ureg->sirfsoc_int_en_reg) &  in sirfsoc_uart_handle_rx_done()
628 	intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);  in sirfsoc_uart_isr()
630 	intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);  in sirfsoc_uart_isr()
656 		cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &  in sirfsoc_uart_isr()
689 				(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &  in sirfsoc_uart_isr()
713 		if (rd_regl(port, ureg->sirfsoc_int_en_reg) &  in sirfsoc_uart_rx_dma_complete_tl()
746 		rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &  in sirfsoc_uart_start_next_rx_dma()
753 				rd_regl(port, ureg->sirfsoc_int_en_reg) |  in sirfsoc_uart_start_next_rx_dma()
775 				rd_regl(port, ureg->sirfsoc_int_en_reg) |  in sirfsoc_uart_start_rx()
974 	txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op);  in sirfsoc_uart_set_termios()
1070 		rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) |  in sirfsoc_uart_startup()
1073 		rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |  in sirfsoc_uart_startup()
1227 	while (rd_regl(port,  in sirfsoc_uart_console_putchar()