Lines Matching refs:tup
138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, in tegra_uart_read() argument
144 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, in tegra_uart_write() argument
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
160 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_get_mctrl() local
171 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
176 static void set_rts(struct tegra_uart_port *tup, bool active) in set_rts() argument
180 mcr = tup->mcr_shadow; in set_rts()
185 if (mcr != tup->mcr_shadow) { in set_rts()
186 tegra_uart_write(tup, mcr, UART_MCR); in set_rts()
187 tup->mcr_shadow = mcr; in set_rts()
192 static void set_dtr(struct tegra_uart_port *tup, bool active) in set_dtr() argument
196 mcr = tup->mcr_shadow; in set_dtr()
201 if (mcr != tup->mcr_shadow) { in set_dtr()
202 tegra_uart_write(tup, mcr, UART_MCR); in set_dtr()
203 tup->mcr_shadow = mcr; in set_dtr()
210 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_mctrl() local
214 mcr = tup->mcr_shadow; in tegra_uart_set_mctrl()
215 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
216 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
219 set_dtr(tup, dtr_enable); in tegra_uart_set_mctrl()
225 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_break_ctl() local
228 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
233 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_break_ctl()
234 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
238 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, in tegra_uart_wait_sym_time() argument
241 if (tup->current_baud) in tegra_uart_wait_sym_time()
242 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
243 tup->current_baud)); in tegra_uart_wait_sym_time()
246 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) in tegra_uart_fifo_reset() argument
248 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
250 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
252 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
255 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
258 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
260 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
264 tegra_uart_read(tup, UART_SCR); in tegra_uart_fifo_reset()
267 tegra_uart_wait_sym_time(tup, 1); in tegra_uart_fifo_reset()
270 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) in tegra_set_baudrate() argument
277 if (tup->current_baud == baud) in tegra_set_baudrate()
280 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
282 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
284 dev_err(tup->uport.dev, in tegra_set_baudrate()
290 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
294 lcr = tup->lcr_shadow; in tegra_set_baudrate()
296 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
298 tegra_uart_write(tup, divisor & 0xFF, UART_TX); in tegra_set_baudrate()
299 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); in tegra_set_baudrate()
302 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
305 tegra_uart_read(tup, UART_SCR); in tegra_set_baudrate()
307 tup->current_baud = baud; in tegra_set_baudrate()
310 tegra_uart_wait_sym_time(tup, 2); in tegra_set_baudrate()
314 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, in tegra_uart_decode_rx_error() argument
323 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
324 dev_err(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
328 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
329 dev_err(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
332 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
333 dev_err(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
335 dev_err(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
336 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
339 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); in tegra_uart_decode_rx_error()
355 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) in tegra_uart_fill_tx_fifo() argument
357 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_fill_tx_fifo()
362 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
363 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fill_tx_fifo()
367 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); in tegra_uart_fill_tx_fifo()
369 tup->uport.icount.tx++; in tegra_uart_fill_tx_fifo()
373 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, in tegra_uart_start_pio_tx() argument
379 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
380 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
381 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
382 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
387 struct tegra_uart_port *tup = args; in tegra_uart_tx_dma_complete() local
388 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_tx_dma_complete()
393 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state); in tegra_uart_tx_dma_complete()
394 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
395 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
396 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
398 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
400 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
401 tegra_uart_start_next_tx(tup); in tegra_uart_tx_dma_complete()
402 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
405 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, in tegra_uart_start_tx_dma() argument
408 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_tx_dma()
411 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_start_tx_dma()
414 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
415 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; in tegra_uart_start_tx_dma()
416 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
417 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
419 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
420 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
424 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
425 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
426 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
427 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
428 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
429 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
433 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) in tegra_uart_start_next_tx() argument
437 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_next_tx()
445 tegra_uart_start_pio_tx(tup, count); in tegra_uart_start_next_tx()
447 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); in tegra_uart_start_next_tx()
449 tegra_uart_start_tx_dma(tup, count); in tegra_uart_start_next_tx()
455 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_start_tx() local
458 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) in tegra_uart_start_tx()
459 tegra_uart_start_next_tx(tup); in tegra_uart_start_tx()
464 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_tx_empty() local
469 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
470 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_tx_empty()
480 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_tx() local
481 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_stop_tx()
485 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
488 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
489 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
490 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
491 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
493 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
497 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) in tegra_uart_handle_tx_pio() argument
499 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_handle_tx_pio()
501 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
502 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
504 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
505 tegra_uart_start_next_tx(tup); in tegra_uart_handle_tx_pio()
509 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, in tegra_uart_handle_rx_pio() argument
517 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_handle_rx_pio()
521 flag = tegra_uart_decode_rx_error(tup, lsr); in tegra_uart_handle_rx_pio()
522 ch = (unsigned char) tegra_uart_read(tup, UART_RX); in tegra_uart_handle_rx_pio()
523 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
525 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) in tegra_uart_handle_rx_pio()
532 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, in tegra_uart_copy_rx_to_tty() argument
537 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
539 dev_err(tup->uport.dev, "No tty port\n"); in tegra_uart_copy_rx_to_tty()
542 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
545 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
548 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
550 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
556 struct tegra_uart_port *tup = args; in tegra_uart_rx_dma_complete() local
557 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
558 int count = tup->rx_bytes_requested; in tegra_uart_rx_dma_complete()
559 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in tegra_uart_rx_dma_complete()
563 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_dma_complete()
567 if (tup->rts_active) in tegra_uart_rx_dma_complete()
568 set_rts(tup, false); in tegra_uart_rx_dma_complete()
572 tegra_uart_copy_rx_to_tty(tup, port, count); in tegra_uart_rx_dma_complete()
574 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_rx_dma_complete()
581 tegra_uart_start_rx_dma(tup); in tegra_uart_rx_dma_complete()
584 if (tup->rts_active) in tegra_uart_rx_dma_complete()
585 set_rts(tup, true); in tegra_uart_rx_dma_complete()
590 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup, in tegra_uart_handle_rx_dma() argument
594 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in tegra_uart_handle_rx_dma()
595 struct tty_port *port = &tup->uport.state->port; in tegra_uart_handle_rx_dma()
596 struct uart_port *u = &tup->uport; in tegra_uart_handle_rx_dma()
600 if (tup->rts_active) in tegra_uart_handle_rx_dma()
601 set_rts(tup, false); in tegra_uart_handle_rx_dma()
603 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_handle_rx_dma()
604 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_handle_rx_dma()
605 async_tx_ack(tup->rx_dma_desc); in tegra_uart_handle_rx_dma()
606 count = tup->rx_bytes_requested - state.residue; in tegra_uart_handle_rx_dma()
610 tegra_uart_copy_rx_to_tty(tup, port, count); in tegra_uart_handle_rx_dma()
612 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_handle_rx_dma()
619 tegra_uart_start_rx_dma(tup); in tegra_uart_handle_rx_dma()
621 if (tup->rts_active) in tegra_uart_handle_rx_dma()
622 set_rts(tup, true); in tegra_uart_handle_rx_dma()
625 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) in tegra_uart_start_rx_dma() argument
629 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
630 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
632 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
633 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
637 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
638 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
639 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_start_rx_dma()
641 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
642 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
643 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
649 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_handle_modem_signal_change() local
652 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_handle_modem_signal_change()
657 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
659 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
662 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
665 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
671 struct tegra_uart_port *tup = data; in tegra_uart_isr() local
672 struct uart_port *u = &tup->uport; in tegra_uart_isr()
680 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_isr()
683 tegra_uart_handle_rx_dma(tup, &flags); in tegra_uart_isr()
684 if (tup->rx_in_progress) { in tegra_uart_isr()
685 ier = tup->ier_shadow; in tegra_uart_isr()
688 tup->ier_shadow = ier; in tegra_uart_isr()
689 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
702 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
703 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
704 tegra_uart_handle_tx_pio(tup); in tegra_uart_isr()
713 ier = tup->ier_shadow; in tegra_uart_isr()
715 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
718 tup->ier_shadow = ier; in tegra_uart_isr()
719 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
724 tegra_uart_decode_rx_error(tup, in tegra_uart_isr()
725 tegra_uart_read(tup, UART_LSR)); in tegra_uart_isr()
737 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_rx() local
744 if (tup->rts_active) in tegra_uart_stop_rx()
745 set_rts(tup, false); in tegra_uart_stop_rx()
747 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
750 tty = tty_port_tty_get(&tup->uport.state->port); in tegra_uart_stop_rx()
752 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ in tegra_uart_stop_rx()
754 ier = tup->ier_shadow; in tegra_uart_stop_rx()
757 tup->ier_shadow = ier; in tegra_uart_stop_rx()
758 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_stop_rx()
759 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
760 if (tup->rx_dma_chan) { in tegra_uart_stop_rx()
761 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_stop_rx()
762 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_stop_rx()
763 async_tx_ack(tup->rx_dma_desc); in tegra_uart_stop_rx()
764 count = tup->rx_bytes_requested - state.residue; in tegra_uart_stop_rx()
765 tegra_uart_copy_rx_to_tty(tup, port, count); in tegra_uart_stop_rx()
766 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_stop_rx()
768 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_stop_rx()
777 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) in tegra_uart_hw_deinit() argument
780 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
781 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
788 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_hw_deinit()
790 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
792 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
793 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
795 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
804 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
805 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
808 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
812 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
816 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
818 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); in tegra_uart_hw_deinit()
819 tup->current_baud = 0; in tegra_uart_hw_deinit()
820 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
822 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
825 static int tegra_uart_hw_init(struct tegra_uart_port *tup) in tegra_uart_hw_init() argument
829 tup->fcr_shadow = 0; in tegra_uart_hw_init()
830 tup->mcr_shadow = 0; in tegra_uart_hw_init()
831 tup->lcr_shadow = 0; in tegra_uart_hw_init()
832 tup->ier_shadow = 0; in tegra_uart_hw_init()
833 tup->current_baud = 0; in tegra_uart_hw_init()
835 clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
838 reset_control_assert(tup->rst); in tegra_uart_hw_init()
840 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
842 tup->rx_in_progress = 0; in tegra_uart_hw_init()
843 tup->tx_in_progress = 0; in tegra_uart_hw_init()
863 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
864 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
865 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
866 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
873 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
874 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); in tegra_uart_hw_init()
875 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
876 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
878 ret = tegra_uart_start_rx_dma(tup); in tegra_uart_hw_init()
880 dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); in tegra_uart_hw_init()
883 tup->rx_in_progress = 1; in tegra_uart_hw_init()
903 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
904 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
908 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, in tegra_uart_dma_channel_allocate() argument
917 dma_chan = dma_request_slave_channel_reason(tup->uport.dev, in tegra_uart_dma_channel_allocate()
921 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
927 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
931 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
937 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
938 tup->uport.state->xmit.buf, UART_XMIT_SIZE, in tegra_uart_dma_channel_allocate()
940 dma_buf = tup->uport.state->xmit.buf; in tegra_uart_dma_channel_allocate()
944 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
948 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
955 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
961 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
962 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
963 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
965 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
966 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
967 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
976 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, in tegra_uart_dma_channel_free() argument
982 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
983 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
984 dma_chan = tup->rx_dma_chan; in tegra_uart_dma_channel_free()
985 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
986 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
987 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
989 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
991 dma_chan = tup->tx_dma_chan; in tegra_uart_dma_channel_free()
992 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
993 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
994 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1001 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_startup() local
1004 ret = tegra_uart_dma_channel_allocate(tup, false); in tegra_uart_startup()
1010 ret = tegra_uart_dma_channel_allocate(tup, true); in tegra_uart_startup()
1016 ret = tegra_uart_hw_init(tup); in tegra_uart_startup()
1023 dev_name(u->dev), tup); in tegra_uart_startup()
1031 tegra_uart_dma_channel_free(tup, true); in tegra_uart_startup()
1033 tegra_uart_dma_channel_free(tup, false); in tegra_uart_startup()
1043 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_flush_buffer() local
1045 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1046 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1047 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1053 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_shutdown() local
1055 tegra_uart_hw_deinit(tup); in tegra_uart_shutdown()
1057 tup->rx_in_progress = 0; in tegra_uart_shutdown()
1058 tup->tx_in_progress = 0; in tegra_uart_shutdown()
1060 tegra_uart_dma_channel_free(tup, true); in tegra_uart_shutdown()
1061 tegra_uart_dma_channel_free(tup, false); in tegra_uart_shutdown()
1062 free_irq(u->irq, tup); in tegra_uart_shutdown()
1069 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_enable_ms() local
1071 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1072 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1073 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1080 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_termios() local
1085 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1087 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1093 if (tup->rts_active) in tegra_uart_set_termios()
1094 set_rts(tup, false); in tegra_uart_set_termios()
1097 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1098 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1099 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_set_termios()
1100 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1103 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1151 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_set_termios()
1152 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1153 tup->symb_bit = symb_bit; in tegra_uart_set_termios()
1160 tegra_set_baudrate(tup, baud); in tegra_uart_set_termios()
1167 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1168 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1169 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1171 if (tup->rts_active) in tegra_uart_set_termios()
1172 set_rts(tup, true); in tegra_uart_set_termios()
1174 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1175 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1176 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1183 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1186 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1187 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1225 struct tegra_uart_port *tup) in tegra_uart_parse_dt() argument
1235 tup->uport.line = port; in tegra_uart_parse_dt()
1237 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1268 struct tegra_uart_port *tup; in tegra_uart_probe() local
1282 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1283 if (!tup) { in tegra_uart_probe()
1288 ret = tegra_uart_parse_dt(pdev, tup); in tegra_uart_probe()
1292 u = &tup->uport; in tegra_uart_probe()
1297 tup->cdata = cdata; in tegra_uart_probe()
1299 platform_set_drvdata(pdev, tup); in tegra_uart_probe()
1311 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1312 if (IS_ERR(tup->uart_clk)) { in tegra_uart_probe()
1314 return PTR_ERR(tup->uart_clk); in tegra_uart_probe()
1317 tup->rst = devm_reset_control_get(&pdev->dev, "serial"); in tegra_uart_probe()
1318 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1320 return PTR_ERR(tup->rst); in tegra_uart_probe()
1336 struct tegra_uart_port *tup = platform_get_drvdata(pdev); in tegra_uart_remove() local
1337 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1346 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_suspend() local
1347 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1354 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_resume() local
1355 struct uart_port *u = &tup->uport; in tegra_uart_resume()