Lines Matching refs:port
113 struct uart_port port[SCCNXP_MAX_UARTS]; member
215 static inline u8 sccnxp_read(struct uart_port *port, u8 reg) in sccnxp_read() argument
217 return readb(port->membase + (reg << port->regshift)); in sccnxp_read()
220 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) in sccnxp_write() argument
222 writeb(v, port->membase + (reg << port->regshift)); in sccnxp_write()
225 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) in sccnxp_port_read() argument
227 return sccnxp_read(port, (port->line << 3) + reg); in sccnxp_port_read()
230 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) in sccnxp_port_write() argument
232 sccnxp_write(port, (port->line << 3) + reg, v); in sccnxp_port_write()
284 static int sccnxp_set_baud(struct uart_port *port, int baud) in sccnxp_set_baud() argument
286 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_set_baud()
296 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); in sccnxp_set_baud()
309 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); in sccnxp_set_baud()
310 sccnxp_port_write(port, SCCNXP_MR_REG, mr0); in sccnxp_set_baud()
313 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); in sccnxp_set_baud()
314 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); in sccnxp_set_baud()
317 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", in sccnxp_set_baud()
323 static void sccnxp_enable_irq(struct uart_port *port, int mask) in sccnxp_enable_irq() argument
325 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_enable_irq()
327 s->imr |= mask << (port->line * 4); in sccnxp_enable_irq()
328 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); in sccnxp_enable_irq()
331 static void sccnxp_disable_irq(struct uart_port *port, int mask) in sccnxp_disable_irq() argument
333 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_disable_irq()
335 s->imr &= ~(mask << (port->line * 4)); in sccnxp_disable_irq()
336 sccnxp_write(port, SCCNXP_IMR_REG, s->imr); in sccnxp_disable_irq()
339 static void sccnxp_set_bit(struct uart_port *port, int sig, int state) in sccnxp_set_bit() argument
342 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_set_bit()
344 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { in sccnxp_set_bit()
345 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); in sccnxp_set_bit()
347 sccnxp_write(port, SCCNXP_SOP_REG, bitmask); in sccnxp_set_bit()
349 sccnxp_write(port, SCCNXP_ROP_REG, bitmask); in sccnxp_set_bit()
353 static void sccnxp_handle_rx(struct uart_port *port) in sccnxp_handle_rx() argument
359 sr = sccnxp_port_read(port, SCCNXP_SR_REG); in sccnxp_handle_rx()
364 ch = sccnxp_port_read(port, SCCNXP_RHR_REG); in sccnxp_handle_rx()
366 port->icount.rx++; in sccnxp_handle_rx()
371 port->icount.brk++; in sccnxp_handle_rx()
372 sccnxp_port_write(port, SCCNXP_CR_REG, in sccnxp_handle_rx()
374 if (uart_handle_break(port)) in sccnxp_handle_rx()
377 port->icount.parity++; in sccnxp_handle_rx()
379 port->icount.frame++; in sccnxp_handle_rx()
381 port->icount.overrun++; in sccnxp_handle_rx()
382 sccnxp_port_write(port, SCCNXP_CR_REG, in sccnxp_handle_rx()
386 sr &= port->read_status_mask; in sccnxp_handle_rx()
397 if (uart_handle_sysrq_char(port, ch)) in sccnxp_handle_rx()
400 if (sr & port->ignore_status_mask) in sccnxp_handle_rx()
403 uart_insert_char(port, sr, SR_OVR, ch, flag); in sccnxp_handle_rx()
406 tty_flip_buffer_push(&port->state->port); in sccnxp_handle_rx()
409 static void sccnxp_handle_tx(struct uart_port *port) in sccnxp_handle_tx() argument
412 struct circ_buf *xmit = &port->state->xmit; in sccnxp_handle_tx()
413 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_handle_tx()
415 if (unlikely(port->x_char)) { in sccnxp_handle_tx()
416 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); in sccnxp_handle_tx()
417 port->icount.tx++; in sccnxp_handle_tx()
418 port->x_char = 0; in sccnxp_handle_tx()
422 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { in sccnxp_handle_tx()
424 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { in sccnxp_handle_tx()
425 sccnxp_disable_irq(port, IMR_TXRDY); in sccnxp_handle_tx()
429 sccnxp_set_bit(port, DIR_OP, 0); in sccnxp_handle_tx()
435 sr = sccnxp_port_read(port, SCCNXP_SR_REG); in sccnxp_handle_tx()
439 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); in sccnxp_handle_tx()
441 port->icount.tx++; in sccnxp_handle_tx()
445 uart_write_wakeup(port); in sccnxp_handle_tx()
454 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); in sccnxp_handle_events()
461 sccnxp_handle_rx(&s->port[i]); in sccnxp_handle_events()
463 sccnxp_handle_tx(&s->port[i]); in sccnxp_handle_events()
492 static void sccnxp_start_tx(struct uart_port *port) in sccnxp_start_tx() argument
494 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_start_tx()
501 sccnxp_set_bit(port, DIR_OP, 1); in sccnxp_start_tx()
503 sccnxp_enable_irq(port, IMR_TXRDY); in sccnxp_start_tx()
508 static void sccnxp_stop_tx(struct uart_port *port) in sccnxp_stop_tx() argument
513 static void sccnxp_stop_rx(struct uart_port *port) in sccnxp_stop_rx() argument
515 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_stop_rx()
519 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); in sccnxp_stop_rx()
523 static unsigned int sccnxp_tx_empty(struct uart_port *port) in sccnxp_tx_empty() argument
527 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_tx_empty()
530 val = sccnxp_port_read(port, SCCNXP_SR_REG); in sccnxp_tx_empty()
536 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) in sccnxp_set_mctrl() argument
538 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_set_mctrl()
546 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); in sccnxp_set_mctrl()
547 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); in sccnxp_set_mctrl()
552 static unsigned int sccnxp_get_mctrl(struct uart_port *port) in sccnxp_get_mctrl() argument
556 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_get_mctrl()
564 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); in sccnxp_get_mctrl()
566 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { in sccnxp_get_mctrl()
567 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], in sccnxp_get_mctrl()
572 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { in sccnxp_get_mctrl()
573 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], in sccnxp_get_mctrl()
578 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { in sccnxp_get_mctrl()
579 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], in sccnxp_get_mctrl()
584 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { in sccnxp_get_mctrl()
585 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], in sccnxp_get_mctrl()
596 static void sccnxp_break_ctl(struct uart_port *port, int break_state) in sccnxp_break_ctl() argument
598 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_break_ctl()
602 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? in sccnxp_break_ctl()
607 static void sccnxp_set_termios(struct uart_port *port, in sccnxp_set_termios() argument
610 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_set_termios()
621 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | in sccnxp_set_termios()
623 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); in sccnxp_set_termios()
624 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); in sccnxp_set_termios()
625 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); in sccnxp_set_termios()
655 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); in sccnxp_set_termios()
656 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); in sccnxp_set_termios()
657 sccnxp_port_write(port, SCCNXP_MR_REG, mr2); in sccnxp_set_termios()
660 port->read_status_mask = SR_OVR; in sccnxp_set_termios()
662 port->read_status_mask |= SR_PE | SR_FE; in sccnxp_set_termios()
664 port->read_status_mask |= SR_BRK; in sccnxp_set_termios()
667 port->ignore_status_mask = 0; in sccnxp_set_termios()
669 port->ignore_status_mask |= SR_BRK; in sccnxp_set_termios()
671 port->ignore_status_mask |= SR_PE; in sccnxp_set_termios()
673 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; in sccnxp_set_termios()
676 baud = uart_get_baud_rate(port, termios, old, 50, in sccnxp_set_termios()
679 baud = sccnxp_set_baud(port, baud); in sccnxp_set_termios()
682 uart_update_timeout(port, termios->c_cflag, baud); in sccnxp_set_termios()
689 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); in sccnxp_set_termios()
694 static int sccnxp_startup(struct uart_port *port) in sccnxp_startup() argument
696 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_startup()
703 sccnxp_write(port, SCCNXP_OPCR_REG, 0); in sccnxp_startup()
707 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); in sccnxp_startup()
708 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); in sccnxp_startup()
709 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); in sccnxp_startup()
710 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); in sccnxp_startup()
713 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); in sccnxp_startup()
716 sccnxp_enable_irq(port, IMR_RXRDY); in sccnxp_startup()
718 s->opened[port->line] = 1; in sccnxp_startup()
725 static void sccnxp_shutdown(struct uart_port *port) in sccnxp_shutdown() argument
727 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_shutdown()
732 s->opened[port->line] = 0; in sccnxp_shutdown()
735 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); in sccnxp_shutdown()
738 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); in sccnxp_shutdown()
742 sccnxp_set_bit(port, DIR_OP, 0); in sccnxp_shutdown()
747 static const char *sccnxp_type(struct uart_port *port) in sccnxp_type() argument
749 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_type()
751 return (port->type == PORT_SC26XX) ? s->chip->name : NULL; in sccnxp_type()
754 static void sccnxp_release_port(struct uart_port *port) in sccnxp_release_port() argument
759 static int sccnxp_request_port(struct uart_port *port) in sccnxp_request_port() argument
765 static void sccnxp_config_port(struct uart_port *port, int flags) in sccnxp_config_port() argument
768 port->type = PORT_SC26XX; in sccnxp_config_port()
771 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) in sccnxp_verify_port() argument
775 if (s->irq == port->irq) in sccnxp_verify_port()
800 static void sccnxp_console_putchar(struct uart_port *port, int c) in sccnxp_console_putchar() argument
805 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { in sccnxp_console_putchar()
806 sccnxp_port_write(port, SCCNXP_THR_REG, c); in sccnxp_console_putchar()
816 struct uart_port *port = &s->port[co->index]; in sccnxp_console_write() local
820 uart_console_write(port, c, n, sccnxp_console_putchar); in sccnxp_console_write()
827 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; in sccnxp_console_setup() local
833 return uart_set_options(port, co, baud, parity, bits, flow); in sccnxp_console_setup()
943 s->port[i].line = i; in sccnxp_probe()
944 s->port[i].dev = &pdev->dev; in sccnxp_probe()
945 s->port[i].irq = s->irq; in sccnxp_probe()
946 s->port[i].type = PORT_SC26XX; in sccnxp_probe()
947 s->port[i].fifosize = s->chip->fifosize; in sccnxp_probe()
948 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; in sccnxp_probe()
949 s->port[i].iotype = UPIO_MEM; in sccnxp_probe()
950 s->port[i].mapbase = res->start; in sccnxp_probe()
951 s->port[i].membase = membase; in sccnxp_probe()
952 s->port[i].regshift = s->pdata.reg_shift; in sccnxp_probe()
953 s->port[i].uartclk = uartclk; in sccnxp_probe()
954 s->port[i].ops = &sccnxp_ops; in sccnxp_probe()
955 uart_add_one_port(&s->uart, &s->port[i]); in sccnxp_probe()
958 sccnxp_set_bit(&s->port[i], DIR_OP, 0); in sccnxp_probe()
963 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); in sccnxp_probe()
1002 uart_remove_one_port(&s->uart, &s->port[i]); in sccnxp_remove()