67 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);  in wait_for_xmitr()
75 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_tx()
83 	msm_write(port, msm_port->imr, UART_IMR);  in msm_start_tx()
91 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_rx()
99 	msm_write(port, msm_port->imr, UART_IMR);  in msm_enable_ms()
112 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in handle_rx_dm()
169 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in handle_rx_dm()
170 	msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in handle_rx_dm()
171 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in handle_rx_dm()
186 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in handle_rx()
230 	msm_write(port, count, UARTDM_NCF_TX);  in reset_dm_count()
295 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in handle_delta_cts()
308 	msm_write(port, 0, UART_IMR); /* disable interrupt */  in msm_irq()
312 		msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);  in msm_irq()
326 	msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */  in msm_irq()
347 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
348 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
349 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
350 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
351 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
352 	msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);  in msm_reset()
356 		msm_write(port, 0, UARTDM_DMEN);  in msm_reset()
367 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
368 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
371 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
378 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
380 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
430 	msm_write(port, entry->code, UART_CSR);  in msm_set_baud_rate()
437 	msm_write(port, watermark, UART_IPR);  in msm_set_baud_rate()
441 	msm_write(port, watermark, UART_RFWR);  in msm_set_baud_rate()
444 	msm_write(port, 10, UART_TFWR);  in msm_set_baud_rate()
446 	msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_set_baud_rate()
450 	msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);  in msm_set_baud_rate()
456 	msm_write(port, msm_port->imr, UART_IMR);  in msm_set_baud_rate()
459 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
460 		msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_set_baud_rate()
461 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
503 	msm_write(port, data, UART_MR1);  in msm_startup()
512 	msm_write(port, 0, UART_IMR); /* disable interrupts */  in msm_shutdown()
571 	msm_write(port, mr, UART_MR2);  in msm_set_termios()
580 	msm_write(port, mr, UART_MR1);  in msm_set_termios()
716 			msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);  in msm_poll_get_char_dm()
720 			msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_poll_get_char_dm()
721 			msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_poll_get_char_dm()
722 			msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,  in msm_poll_get_char_dm()
745 	msm_write(port, 0, UART_IMR);  in msm_poll_get_char()
753 	msm_write(port, imr, UART_IMR);  in msm_poll_get_char()
765 	msm_write(port, 0, UART_IMR);  in msm_poll_put_char()
775 	msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);  in msm_poll_put_char()
782 	msm_write(port, imr, UART_IMR);  in msm_poll_put_char()