Lines Matching refs:pi
321 static void mpsc_start_rx(struct mpsc_port_info *pi);
322 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
331 static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) in mpsc_brg_init() argument
335 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_init()
338 if (pi->brg_can_tune) in mpsc_brg_init()
341 if (pi->mirror_regs) in mpsc_brg_init()
342 pi->BRG_BCR_m = v; in mpsc_brg_init()
343 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_init()
345 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, in mpsc_brg_init()
346 pi->brg_base + BRG_BTR); in mpsc_brg_init()
349 static void mpsc_brg_enable(struct mpsc_port_info *pi) in mpsc_brg_enable() argument
353 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_enable()
356 if (pi->mirror_regs) in mpsc_brg_enable()
357 pi->BRG_BCR_m = v; in mpsc_brg_enable()
358 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_enable()
361 static void mpsc_brg_disable(struct mpsc_port_info *pi) in mpsc_brg_disable() argument
365 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_brg_disable()
368 if (pi->mirror_regs) in mpsc_brg_disable()
369 pi->BRG_BCR_m = v; in mpsc_brg_disable()
370 writel(v, pi->brg_base + BRG_BCR); in mpsc_brg_disable()
382 static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) in mpsc_set_baudrate() argument
384 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; in mpsc_set_baudrate()
387 mpsc_brg_disable(pi); in mpsc_set_baudrate()
388 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); in mpsc_set_baudrate()
391 if (pi->mirror_regs) in mpsc_set_baudrate()
392 pi->BRG_BCR_m = v; in mpsc_set_baudrate()
393 writel(v, pi->brg_base + BRG_BCR); in mpsc_set_baudrate()
394 mpsc_brg_enable(pi); in mpsc_set_baudrate()
405 static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size) in mpsc_sdma_burstsize() argument
410 pi->port.line, burst_size); in mpsc_sdma_burstsize()
423 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), in mpsc_sdma_burstsize()
424 pi->sdma_base + SDMA_SDC); in mpsc_sdma_burstsize()
427 static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size) in mpsc_sdma_init() argument
429 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, in mpsc_sdma_init()
432 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, in mpsc_sdma_init()
433 pi->sdma_base + SDMA_SDC); in mpsc_sdma_init()
434 mpsc_sdma_burstsize(pi, burst_size); in mpsc_sdma_init()
437 static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask) in mpsc_sdma_intr_mask() argument
441 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask); in mpsc_sdma_intr_mask()
443 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : in mpsc_sdma_intr_mask()
444 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_mask()
447 if (pi->port.line) in mpsc_sdma_intr_mask()
451 if (pi->mirror_regs) in mpsc_sdma_intr_mask()
452 pi->shared_regs->SDMA_INTR_MASK_m = v; in mpsc_sdma_intr_mask()
453 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_mask()
455 if (pi->port.line) in mpsc_sdma_intr_mask()
460 static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask) in mpsc_sdma_intr_unmask() argument
464 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); in mpsc_sdma_intr_unmask()
466 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m in mpsc_sdma_intr_unmask()
467 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_unmask()
470 if (pi->port.line) in mpsc_sdma_intr_unmask()
474 if (pi->mirror_regs) in mpsc_sdma_intr_unmask()
475 pi->shared_regs->SDMA_INTR_MASK_m = v; in mpsc_sdma_intr_unmask()
476 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); in mpsc_sdma_intr_unmask()
479 static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi) in mpsc_sdma_intr_ack() argument
481 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); in mpsc_sdma_intr_ack()
483 if (pi->mirror_regs) in mpsc_sdma_intr_ack()
484 pi->shared_regs->SDMA_INTR_CAUSE_m = 0; in mpsc_sdma_intr_ack()
485 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE in mpsc_sdma_intr_ack()
486 + pi->port.line); in mpsc_sdma_intr_ack()
489 static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, in mpsc_sdma_set_rx_ring() argument
493 pi->port.line, (u32)rxre_p); in mpsc_sdma_set_rx_ring()
495 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); in mpsc_sdma_set_rx_ring()
498 static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, in mpsc_sdma_set_tx_ring() argument
501 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); in mpsc_sdma_set_tx_ring()
502 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); in mpsc_sdma_set_tx_ring()
505 static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val) in mpsc_sdma_cmd() argument
509 v = readl(pi->sdma_base + SDMA_SDCM); in mpsc_sdma_cmd()
515 writel(v, pi->sdma_base + SDMA_SDCM); in mpsc_sdma_cmd()
519 static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi) in mpsc_sdma_tx_active() argument
521 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; in mpsc_sdma_tx_active()
524 static void mpsc_sdma_start_tx(struct mpsc_port_info *pi) in mpsc_sdma_start_tx() argument
529 if (!mpsc_sdma_tx_active(pi)) { in mpsc_sdma_start_tx()
530 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_sdma_start_tx()
531 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_sdma_start_tx()
532 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_sdma_start_tx()
535 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_sdma_start_tx()
542 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_sdma_start_tx()
544 mpsc_sdma_set_tx_ring(pi, txre_p); in mpsc_sdma_start_tx()
545 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); in mpsc_sdma_start_tx()
550 static void mpsc_sdma_stop(struct mpsc_port_info *pi) in mpsc_sdma_stop() argument
552 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); in mpsc_sdma_stop()
555 mpsc_sdma_cmd(pi, 0); in mpsc_sdma_stop()
556 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT); in mpsc_sdma_stop()
559 mpsc_sdma_set_tx_ring(pi, NULL); in mpsc_sdma_stop()
560 mpsc_sdma_set_rx_ring(pi, NULL); in mpsc_sdma_stop()
563 mpsc_sdma_intr_mask(pi, 0xf); in mpsc_sdma_stop()
564 mpsc_sdma_intr_ack(pi); in mpsc_sdma_stop()
575 static void mpsc_hw_init(struct mpsc_port_info *pi) in mpsc_hw_init() argument
579 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line); in mpsc_hw_init()
582 if (pi->mirror_regs) { in mpsc_hw_init()
583 v = pi->shared_regs->MPSC_MRR_m; in mpsc_hw_init()
585 pi->shared_regs->MPSC_MRR_m = v; in mpsc_hw_init()
586 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
588 v = pi->shared_regs->MPSC_RCRR_m; in mpsc_hw_init()
590 pi->shared_regs->MPSC_RCRR_m = v; in mpsc_hw_init()
591 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
593 v = pi->shared_regs->MPSC_TCRR_m; in mpsc_hw_init()
595 pi->shared_regs->MPSC_TCRR_m = v; in mpsc_hw_init()
596 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
598 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
600 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); in mpsc_hw_init()
602 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
604 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); in mpsc_hw_init()
606 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
608 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); in mpsc_hw_init()
612 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL); in mpsc_hw_init()
615 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH); in mpsc_hw_init()
616 mpsc_set_baudrate(pi, pi->default_baud); in mpsc_hw_init()
618 if (pi->mirror_regs) { in mpsc_hw_init()
619 pi->MPSC_CHR_1_m = 0; in mpsc_hw_init()
620 pi->MPSC_CHR_2_m = 0; in mpsc_hw_init()
622 writel(0, pi->mpsc_base + MPSC_CHR_1); in mpsc_hw_init()
623 writel(0, pi->mpsc_base + MPSC_CHR_2); in mpsc_hw_init()
624 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3); in mpsc_hw_init()
625 writel(0, pi->mpsc_base + MPSC_CHR_4); in mpsc_hw_init()
626 writel(0, pi->mpsc_base + MPSC_CHR_5); in mpsc_hw_init()
627 writel(0, pi->mpsc_base + MPSC_CHR_6); in mpsc_hw_init()
628 writel(0, pi->mpsc_base + MPSC_CHR_7); in mpsc_hw_init()
629 writel(0, pi->mpsc_base + MPSC_CHR_8); in mpsc_hw_init()
630 writel(0, pi->mpsc_base + MPSC_CHR_9); in mpsc_hw_init()
631 writel(0, pi->mpsc_base + MPSC_CHR_10); in mpsc_hw_init()
634 static void mpsc_enter_hunt(struct mpsc_port_info *pi) in mpsc_enter_hunt() argument
636 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); in mpsc_enter_hunt()
638 if (pi->mirror_regs) { in mpsc_enter_hunt()
639 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH, in mpsc_enter_hunt()
640 pi->mpsc_base + MPSC_CHR_2); in mpsc_enter_hunt()
644 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, in mpsc_enter_hunt()
645 pi->mpsc_base + MPSC_CHR_2); in mpsc_enter_hunt()
647 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) in mpsc_enter_hunt()
652 static void mpsc_freeze(struct mpsc_port_info *pi) in mpsc_freeze() argument
656 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line); in mpsc_freeze()
658 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_freeze()
659 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_freeze()
662 if (pi->mirror_regs) in mpsc_freeze()
663 pi->MPSC_MPCR_m = v; in mpsc_freeze()
664 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_freeze()
667 static void mpsc_unfreeze(struct mpsc_port_info *pi) in mpsc_unfreeze() argument
671 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_unfreeze()
672 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_unfreeze()
675 if (pi->mirror_regs) in mpsc_unfreeze()
676 pi->MPSC_MPCR_m = v; in mpsc_unfreeze()
677 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_unfreeze()
679 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); in mpsc_unfreeze()
682 static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len) in mpsc_set_char_length() argument
686 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len); in mpsc_set_char_length()
688 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_set_char_length()
689 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_set_char_length()
692 if (pi->mirror_regs) in mpsc_set_char_length()
693 pi->MPSC_MPCR_m = v; in mpsc_set_char_length()
694 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_set_char_length()
697 static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len) in mpsc_set_stop_bit_length() argument
702 pi->port.line, len); in mpsc_set_stop_bit_length()
704 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : in mpsc_set_stop_bit_length()
705 readl(pi->mpsc_base + MPSC_MPCR); in mpsc_set_stop_bit_length()
709 if (pi->mirror_regs) in mpsc_set_stop_bit_length()
710 pi->MPSC_MPCR_m = v; in mpsc_set_stop_bit_length()
711 writel(v, pi->mpsc_base + MPSC_MPCR); in mpsc_set_stop_bit_length()
714 static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p) in mpsc_set_parity() argument
718 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p); in mpsc_set_parity()
720 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m : in mpsc_set_parity()
721 readl(pi->mpsc_base + MPSC_CHR_2); in mpsc_set_parity()
726 if (pi->mirror_regs) in mpsc_set_parity()
727 pi->MPSC_CHR_2_m = v; in mpsc_set_parity()
728 writel(v, pi->mpsc_base + MPSC_CHR_2); in mpsc_set_parity()
739 static void mpsc_init_hw(struct mpsc_port_info *pi) in mpsc_init_hw() argument
741 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); in mpsc_init_hw()
743 mpsc_brg_init(pi, pi->brg_clk_src); in mpsc_init_hw()
744 mpsc_brg_enable(pi); in mpsc_init_hw()
745 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ in mpsc_init_hw()
746 mpsc_sdma_stop(pi); in mpsc_init_hw()
747 mpsc_hw_init(pi); in mpsc_init_hw()
750 static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi) in mpsc_alloc_ring_mem() argument
755 pi->port.line); in mpsc_alloc_ring_mem()
757 if (!pi->dma_region) { in mpsc_alloc_ring_mem()
758 if (!dma_supported(pi->port.dev, 0xffffffff)) { in mpsc_alloc_ring_mem()
761 } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev, in mpsc_alloc_ring_mem()
763 &pi->dma_region_p, GFP_KERNEL)) in mpsc_alloc_ring_mem()
773 static void mpsc_free_ring_mem(struct mpsc_port_info *pi) in mpsc_free_ring_mem() argument
775 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); in mpsc_free_ring_mem()
777 if (pi->dma_region) { in mpsc_free_ring_mem()
778 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE, in mpsc_free_ring_mem()
779 pi->dma_region, pi->dma_region_p); in mpsc_free_ring_mem()
780 pi->dma_region = NULL; in mpsc_free_ring_mem()
781 pi->dma_region_p = (dma_addr_t)NULL; in mpsc_free_ring_mem()
785 static void mpsc_init_rings(struct mpsc_port_info *pi) in mpsc_init_rings() argument
793 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line); in mpsc_init_rings()
795 BUG_ON(pi->dma_region == NULL); in mpsc_init_rings()
797 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE); in mpsc_init_rings()
803 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment()); in mpsc_init_rings()
804 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment()); in mpsc_init_rings()
810 pi->rxr = dp; in mpsc_init_rings()
811 pi->rxr_p = dp_p; in mpsc_init_rings()
815 pi->rxb = (u8 *)dp; in mpsc_init_rings()
816 pi->rxb_p = (u8 *)dp_p; in mpsc_init_rings()
820 pi->rxr_posn = 0; in mpsc_init_rings()
822 pi->txr = dp; in mpsc_init_rings()
823 pi->txr_p = dp_p; in mpsc_init_rings()
827 pi->txb = (u8 *)dp; in mpsc_init_rings()
828 pi->txb_p = (u8 *)dp_p; in mpsc_init_rings()
830 pi->txr_head = 0; in mpsc_init_rings()
831 pi->txr_tail = 0; in mpsc_init_rings()
834 dp = pi->rxr; in mpsc_init_rings()
835 dp_p = pi->rxr_p; in mpsc_init_rings()
836 bp = pi->rxb; in mpsc_init_rings()
837 bp_p = pi->rxb_p; in mpsc_init_rings()
855 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */ in mpsc_init_rings()
858 dp = pi->txr; in mpsc_init_rings()
859 dp_p = pi->txr_p; in mpsc_init_rings()
860 bp = pi->txb; in mpsc_init_rings()
861 bp_p = pi->txb_p; in mpsc_init_rings()
874 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ in mpsc_init_rings()
876 dma_cache_sync(pi->port.dev, (void *)pi->dma_region, in mpsc_init_rings()
879 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_init_rings()
880 flush_dcache_range((ulong)pi->dma_region, in mpsc_init_rings()
881 (ulong)pi->dma_region in mpsc_init_rings()
888 static void mpsc_uninit_rings(struct mpsc_port_info *pi) in mpsc_uninit_rings() argument
890 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); in mpsc_uninit_rings()
892 BUG_ON(pi->dma_region == NULL); in mpsc_uninit_rings()
894 pi->rxr = 0; in mpsc_uninit_rings()
895 pi->rxr_p = 0; in mpsc_uninit_rings()
896 pi->rxb = NULL; in mpsc_uninit_rings()
897 pi->rxb_p = NULL; in mpsc_uninit_rings()
898 pi->rxr_posn = 0; in mpsc_uninit_rings()
900 pi->txr = 0; in mpsc_uninit_rings()
901 pi->txr_p = 0; in mpsc_uninit_rings()
902 pi->txb = NULL; in mpsc_uninit_rings()
903 pi->txb_p = NULL; in mpsc_uninit_rings()
904 pi->txr_head = 0; in mpsc_uninit_rings()
905 pi->txr_tail = 0; in mpsc_uninit_rings()
908 static int mpsc_make_ready(struct mpsc_port_info *pi) in mpsc_make_ready() argument
912 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line); in mpsc_make_ready()
914 if (!pi->ready) { in mpsc_make_ready()
915 mpsc_init_hw(pi); in mpsc_make_ready()
916 if ((rc = mpsc_alloc_ring_mem(pi))) in mpsc_make_ready()
918 mpsc_init_rings(pi); in mpsc_make_ready()
919 pi->ready = 1; in mpsc_make_ready()
937 static int mpsc_rx_intr(struct mpsc_port_info *pi, unsigned long *flags) in mpsc_rx_intr() argument
940 struct tty_port *port = &pi->port.state->port; in mpsc_rx_intr()
946 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); in mpsc_rx_intr()
948 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); in mpsc_rx_intr()
950 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
953 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
973 spin_unlock_irqrestore(&pi->port.lock, *flags); in mpsc_rx_intr()
975 spin_lock_irqsave(&pi->port.lock, *flags); in mpsc_rx_intr()
983 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); in mpsc_rx_intr()
984 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE, in mpsc_rx_intr()
987 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1004 pi->port.icount.rx++; in mpsc_rx_intr()
1007 pi->port.icount.brk++; in mpsc_rx_intr()
1009 if (uart_handle_break(&pi->port)) in mpsc_rx_intr()
1012 pi->port.icount.frame++; in mpsc_rx_intr()
1014 pi->port.icount.overrun++; in mpsc_rx_intr()
1017 cmdstat &= pi->port.read_status_mask; in mpsc_rx_intr()
1029 if (uart_handle_sysrq_char(&pi->port, *bp)) { in mpsc_rx_intr()
1044 && !(cmdstat & pi->port.ignore_status_mask)) { in mpsc_rx_intr()
1050 pi->port.icount.rx += bytes_in; in mpsc_rx_intr()
1060 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
1063 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1069 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); in mpsc_rx_intr()
1071 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE)); in mpsc_rx_intr()
1072 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, in mpsc_rx_intr()
1075 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_rx_intr()
1083 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) in mpsc_rx_intr()
1084 mpsc_start_rx(pi); in mpsc_rx_intr()
1086 spin_unlock_irqrestore(&pi->port.lock, *flags); in mpsc_rx_intr()
1088 spin_lock_irqsave(&pi->port.lock, *flags); in mpsc_rx_intr()
1092 static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr) in mpsc_setup_tx_desc() argument
1096 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_setup_tx_desc()
1097 + (pi->txr_head * MPSC_TXRE_SIZE)); in mpsc_setup_tx_desc()
1106 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_setup_tx_desc()
1109 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_setup_tx_desc()
1115 static void mpsc_copy_tx_data(struct mpsc_port_info *pi) in mpsc_copy_tx_data() argument
1117 struct circ_buf *xmit = &pi->port.state->xmit; in mpsc_copy_tx_data()
1122 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) in mpsc_copy_tx_data()
1124 if (pi->port.x_char) { in mpsc_copy_tx_data()
1133 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_copy_tx_data()
1134 *bp = pi->port.x_char; in mpsc_copy_tx_data()
1135 pi->port.x_char = 0; in mpsc_copy_tx_data()
1138 && !uart_tx_stopped(&pi->port)) { in mpsc_copy_tx_data()
1143 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_copy_tx_data()
1148 uart_write_wakeup(&pi->port); in mpsc_copy_tx_data()
1153 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE, in mpsc_copy_tx_data()
1156 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_copy_tx_data()
1160 mpsc_setup_tx_desc(pi, i, 1); in mpsc_copy_tx_data()
1163 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_copy_tx_data()
1167 static int mpsc_tx_intr(struct mpsc_port_info *pi) in mpsc_tx_intr() argument
1173 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_tx_intr()
1175 if (!mpsc_sdma_tx_active(pi)) { in mpsc_tx_intr()
1176 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_tx_intr()
1177 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_tx_intr()
1179 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE, in mpsc_tx_intr()
1182 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_tx_intr()
1189 pi->port.icount.tx += be16_to_cpu(txre->bytecnt); in mpsc_tx_intr()
1190 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1); in mpsc_tx_intr()
1193 if (pi->txr_head == pi->txr_tail) in mpsc_tx_intr()
1196 txre = (struct mpsc_tx_desc *)(pi->txr in mpsc_tx_intr()
1197 + (pi->txr_tail * MPSC_TXRE_SIZE)); in mpsc_tx_intr()
1198 dma_cache_sync(pi->port.dev, (void *)txre, in mpsc_tx_intr()
1201 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_tx_intr()
1207 mpsc_copy_tx_data(pi); in mpsc_tx_intr()
1208 mpsc_sdma_start_tx(pi); /* start next desc if ready */ in mpsc_tx_intr()
1211 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_tx_intr()
1222 struct mpsc_port_info *pi = dev_id; in mpsc_sdma_intr() local
1226 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line); in mpsc_sdma_intr()
1228 spin_lock_irqsave(&pi->port.lock, iflags); in mpsc_sdma_intr()
1229 mpsc_sdma_intr_ack(pi); in mpsc_sdma_intr()
1230 if (mpsc_rx_intr(pi, &iflags)) in mpsc_sdma_intr()
1232 if (mpsc_tx_intr(pi)) in mpsc_sdma_intr()
1234 spin_unlock_irqrestore(&pi->port.lock, iflags); in mpsc_sdma_intr()
1236 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line); in mpsc_sdma_intr()
1249 struct mpsc_port_info *pi = in mpsc_tx_empty() local
1254 spin_lock_irqsave(&pi->port.lock, iflags); in mpsc_tx_empty()
1255 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT; in mpsc_tx_empty()
1256 spin_unlock_irqrestore(&pi->port.lock, iflags); in mpsc_tx_empty()
1268 struct mpsc_port_info *pi = in mpsc_get_mctrl() local
1272 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m in mpsc_get_mctrl()
1273 : readl(pi->mpsc_base + MPSC_CHR_10); in mpsc_get_mctrl()
1286 struct mpsc_port_info *pi = in mpsc_stop_tx() local
1291 mpsc_freeze(pi); in mpsc_stop_tx()
1296 struct mpsc_port_info *pi = in mpsc_start_tx() local
1300 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_start_tx()
1302 mpsc_unfreeze(pi); in mpsc_start_tx()
1303 mpsc_copy_tx_data(pi); in mpsc_start_tx()
1304 mpsc_sdma_start_tx(pi); in mpsc_start_tx()
1306 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_start_tx()
1311 static void mpsc_start_rx(struct mpsc_port_info *pi) in mpsc_start_rx() argument
1313 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); in mpsc_start_rx()
1315 if (pi->rcv_data) { in mpsc_start_rx()
1316 mpsc_enter_hunt(pi); in mpsc_start_rx()
1317 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); in mpsc_start_rx()
1323 struct mpsc_port_info *pi = in mpsc_stop_rx() local
1328 if (pi->mirror_regs) { in mpsc_stop_rx()
1329 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA, in mpsc_stop_rx()
1330 pi->mpsc_base + MPSC_CHR_2); in mpsc_stop_rx()
1334 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA, in mpsc_stop_rx()
1335 pi->mpsc_base + MPSC_CHR_2); in mpsc_stop_rx()
1337 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA) in mpsc_stop_rx()
1341 mpsc_sdma_cmd(pi, SDMA_SDCM_AR); in mpsc_stop_rx()
1346 struct mpsc_port_info *pi = in mpsc_break_ctl() local
1353 spin_lock_irqsave(&pi->port.lock, flags); in mpsc_break_ctl()
1354 if (pi->mirror_regs) in mpsc_break_ctl()
1355 pi->MPSC_CHR_1_m = v; in mpsc_break_ctl()
1356 writel(v, pi->mpsc_base + MPSC_CHR_1); in mpsc_break_ctl()
1357 spin_unlock_irqrestore(&pi->port.lock, flags); in mpsc_break_ctl()
1362 struct mpsc_port_info *pi = in mpsc_startup() local
1368 port->line, pi->port.irq); in mpsc_startup()
1370 if ((rc = mpsc_make_ready(pi)) == 0) { in mpsc_startup()
1372 mpsc_sdma_intr_ack(pi); in mpsc_startup()
1378 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, in mpsc_startup()
1379 "mpsc-sdma", pi)) in mpsc_startup()
1381 pi->port.irq); in mpsc_startup()
1383 mpsc_sdma_intr_unmask(pi, 0xf); in mpsc_startup()
1384 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p in mpsc_startup()
1385 + (pi->rxr_posn * MPSC_RXRE_SIZE))); in mpsc_startup()
1393 struct mpsc_port_info *pi = in mpsc_shutdown() local
1398 mpsc_sdma_stop(pi); in mpsc_shutdown()
1399 free_irq(pi->port.irq, pi); in mpsc_shutdown()
1405 struct mpsc_port_info *pi = in mpsc_set_termios() local
1411 pi->c_iflag = termios->c_iflag; in mpsc_set_termios()
1412 pi->c_cflag = termios->c_cflag; in mpsc_set_termios()
1450 spin_lock_irqsave(&pi->port.lock, flags); in mpsc_set_termios()
1454 mpsc_set_char_length(pi, chr_bits); in mpsc_set_termios()
1455 mpsc_set_stop_bit_length(pi, stop_bits); in mpsc_set_termios()
1456 mpsc_set_parity(pi, par); in mpsc_set_termios()
1457 mpsc_set_baudrate(pi, baud); in mpsc_set_termios()
1460 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; in mpsc_set_termios()
1463 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE in mpsc_set_termios()
1467 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; in mpsc_set_termios()
1470 pi->port.ignore_status_mask = 0; in mpsc_set_termios()
1473 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE in mpsc_set_termios()
1477 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; in mpsc_set_termios()
1480 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR; in mpsc_set_termios()
1484 if (!pi->rcv_data) { in mpsc_set_termios()
1485 pi->rcv_data = 1; in mpsc_set_termios()
1486 mpsc_start_rx(pi); in mpsc_set_termios()
1488 } else if (pi->rcv_data) { in mpsc_set_termios()
1490 pi->rcv_data = 0; in mpsc_set_termios()
1493 spin_unlock_irqrestore(&pi->port.lock, flags); in mpsc_set_termios()
1510 struct mpsc_port_info *pi = in mpsc_release_port() local
1513 if (pi->ready) { in mpsc_release_port()
1514 mpsc_uninit_rings(pi); in mpsc_release_port()
1515 mpsc_free_ring_mem(pi); in mpsc_release_port()
1516 pi->ready = 0; in mpsc_release_port()
1526 struct mpsc_port_info *pi = in mpsc_verify_port() local
1530 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line); in mpsc_verify_port()
1534 else if (pi->port.irq != ser->irq) in mpsc_verify_port()
1538 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */ in mpsc_verify_port()
1540 else if ((void *)pi->port.mapbase != ser->iomem_base) in mpsc_verify_port()
1542 else if (pi->port.iobase != ser->port) in mpsc_verify_port()
1562 struct mpsc_port_info *pi = in mpsc_get_poll_char() local
1571 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); in mpsc_get_poll_char()
1581 rxre = (struct mpsc_rx_desc *)(pi->rxr + in mpsc_get_poll_char()
1582 (pi->rxr_posn*MPSC_RXRE_SIZE)); in mpsc_get_poll_char()
1583 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1586 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1598 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); in mpsc_get_poll_char()
1599 dma_cache_sync(pi->port.dev, (void *) bp, in mpsc_get_poll_char()
1602 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1608 !(cmdstat & pi->port.ignore_status_mask)) { in mpsc_get_poll_char()
1616 pi->port.icount.rx += bytes_in; in mpsc_get_poll_char()
1625 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1628 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1634 pi->rxr_posn = (pi->rxr_posn + 1) & in mpsc_get_poll_char()
1636 rxre = (struct mpsc_rx_desc *)(pi->rxr + in mpsc_get_poll_char()
1637 (pi->rxr_posn * MPSC_RXRE_SIZE)); in mpsc_get_poll_char()
1638 dma_cache_sync(pi->port.dev, (void *)rxre, in mpsc_get_poll_char()
1641 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_get_poll_char()
1648 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) in mpsc_get_poll_char()
1649 mpsc_start_rx(pi); in mpsc_get_poll_char()
1663 struct mpsc_port_info *pi = in mpsc_put_poll_char() local
1667 data = readl(pi->mpsc_base + MPSC_MPCR); in mpsc_put_poll_char()
1668 writeb(c, pi->mpsc_base + MPSC_CHR_1); in mpsc_put_poll_char()
1670 data = readl(pi->mpsc_base + MPSC_CHR_2); in mpsc_put_poll_char()
1672 writel(data, pi->mpsc_base + MPSC_CHR_2); in mpsc_put_poll_char()
1675 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS); in mpsc_put_poll_char()
1712 struct mpsc_port_info *pi = &mpsc_ports[co->index]; in mpsc_console_write() local
1717 spin_lock_irqsave(&pi->tx_lock, iflags); in mpsc_console_write()
1719 while (pi->txr_head != pi->txr_tail) { in mpsc_console_write()
1720 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1722 mpsc_sdma_intr_ack(pi); in mpsc_console_write()
1723 mpsc_tx_intr(pi); in mpsc_console_write()
1726 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1730 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); in mpsc_console_write()
1751 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE, in mpsc_console_write()
1754 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ in mpsc_console_write()
1758 mpsc_setup_tx_desc(pi, i, 0); in mpsc_console_write()
1759 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_console_write()
1760 mpsc_sdma_start_tx(pi); in mpsc_console_write()
1762 while (mpsc_sdma_tx_active(pi)) in mpsc_console_write()
1765 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1); in mpsc_console_write()
1768 spin_unlock_irqrestore(&pi->tx_lock, iflags); in mpsc_console_write()
1773 struct mpsc_port_info *pi; in mpsc_console_setup() local
1781 pi = &mpsc_ports[co->index]; in mpsc_console_setup()
1783 baud = pi->default_baud; in mpsc_console_setup()
1784 bits = pi->default_bits; in mpsc_console_setup()
1785 parity = pi->default_parity; in mpsc_console_setup()
1786 flow = pi->default_flow; in mpsc_console_setup()
1788 if (!pi->port.ops) in mpsc_console_setup()
1791 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */ in mpsc_console_setup()
1796 return uart_set_options(&pi->port, co, baud, parity, bits, flow); in mpsc_console_setup()
1959 static int mpsc_drv_map_regs(struct mpsc_port_info *pi, in mpsc_drv_map_regs() argument
1967 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1968 pi->mpsc_base_p = r->start; in mpsc_drv_map_regs()
1978 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1979 pi->sdma_base_p = r->start; in mpsc_drv_map_regs()
1982 if (pi->mpsc_base) { in mpsc_drv_map_regs()
1983 iounmap(pi->mpsc_base); in mpsc_drv_map_regs()
1984 pi->mpsc_base = NULL; in mpsc_drv_map_regs()
1992 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); in mpsc_drv_map_regs()
1993 pi->brg_base_p = r->start; in mpsc_drv_map_regs()
1996 if (pi->mpsc_base) { in mpsc_drv_map_regs()
1997 iounmap(pi->mpsc_base); in mpsc_drv_map_regs()
1998 pi->mpsc_base = NULL; in mpsc_drv_map_regs()
2000 if (pi->sdma_base) { in mpsc_drv_map_regs()
2001 iounmap(pi->sdma_base); in mpsc_drv_map_regs()
2002 pi->sdma_base = NULL; in mpsc_drv_map_regs()
2012 static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi) in mpsc_drv_unmap_regs() argument
2014 if (!pi->mpsc_base) { in mpsc_drv_unmap_regs()
2015 iounmap(pi->mpsc_base); in mpsc_drv_unmap_regs()
2016 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2018 if (!pi->sdma_base) { in mpsc_drv_unmap_regs()
2019 iounmap(pi->sdma_base); in mpsc_drv_unmap_regs()
2020 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2022 if (!pi->brg_base) { in mpsc_drv_unmap_regs()
2023 iounmap(pi->brg_base); in mpsc_drv_unmap_regs()
2024 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE); in mpsc_drv_unmap_regs()
2027 pi->mpsc_base = NULL; in mpsc_drv_unmap_regs()
2028 pi->sdma_base = NULL; in mpsc_drv_unmap_regs()
2029 pi->brg_base = NULL; in mpsc_drv_unmap_regs()
2031 pi->mpsc_base_p = 0; in mpsc_drv_unmap_regs()
2032 pi->sdma_base_p = 0; in mpsc_drv_unmap_regs()
2033 pi->brg_base_p = 0; in mpsc_drv_unmap_regs()
2036 static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi, in mpsc_drv_get_platform_data() argument
2043 pi->port.uartclk = pdata->brg_clk_freq; in mpsc_drv_get_platform_data()
2044 pi->port.iotype = UPIO_MEM; in mpsc_drv_get_platform_data()
2045 pi->port.line = num; in mpsc_drv_get_platform_data()
2046 pi->port.type = PORT_MPSC; in mpsc_drv_get_platform_data()
2047 pi->port.fifosize = MPSC_TXBE_SIZE; in mpsc_drv_get_platform_data()
2048 pi->port.membase = pi->mpsc_base; in mpsc_drv_get_platform_data()
2049 pi->port.mapbase = (ulong)pi->mpsc_base; in mpsc_drv_get_platform_data()
2050 pi->port.ops = &mpsc_pops; in mpsc_drv_get_platform_data()
2052 pi->mirror_regs = pdata->mirror_regs; in mpsc_drv_get_platform_data()
2053 pi->cache_mgmt = pdata->cache_mgmt; in mpsc_drv_get_platform_data()
2054 pi->brg_can_tune = pdata->brg_can_tune; in mpsc_drv_get_platform_data()
2055 pi->brg_clk_src = pdata->brg_clk_src; in mpsc_drv_get_platform_data()
2056 pi->mpsc_max_idle = pdata->max_idle; in mpsc_drv_get_platform_data()
2057 pi->default_baud = pdata->default_baud; in mpsc_drv_get_platform_data()
2058 pi->default_bits = pdata->default_bits; in mpsc_drv_get_platform_data()
2059 pi->default_parity = pdata->default_parity; in mpsc_drv_get_platform_data()
2060 pi->default_flow = pdata->default_flow; in mpsc_drv_get_platform_data()
2063 pi->MPSC_CHR_1_m = pdata->chr_1_val; in mpsc_drv_get_platform_data()
2064 pi->MPSC_CHR_2_m = pdata->chr_2_val; in mpsc_drv_get_platform_data()
2065 pi->MPSC_CHR_10_m = pdata->chr_10_val; in mpsc_drv_get_platform_data()
2066 pi->MPSC_MPCR_m = pdata->mpcr_val; in mpsc_drv_get_platform_data()
2067 pi->BRG_BCR_m = pdata->bcr_val; in mpsc_drv_get_platform_data()
2069 pi->shared_regs = &mpsc_shared_regs; in mpsc_drv_get_platform_data()
2071 pi->port.irq = platform_get_irq(pd, 0); in mpsc_drv_get_platform_data()
2076 struct mpsc_port_info *pi; in mpsc_drv_probe() local
2082 pi = &mpsc_ports[dev->id]; in mpsc_drv_probe()
2084 if (!(rc = mpsc_drv_map_regs(pi, dev))) { in mpsc_drv_probe()
2085 mpsc_drv_get_platform_data(pi, dev, dev->id); in mpsc_drv_probe()
2086 pi->port.dev = &dev->dev; in mpsc_drv_probe()
2088 if (!(rc = mpsc_make_ready(pi))) { in mpsc_drv_probe()
2089 spin_lock_init(&pi->tx_lock); in mpsc_drv_probe()
2091 &pi->port))) { in mpsc_drv_probe()
2095 pi); in mpsc_drv_probe()
2096 mpsc_drv_unmap_regs(pi); in mpsc_drv_probe()
2099 mpsc_drv_unmap_regs(pi); in mpsc_drv_probe()