183 	out_be32(&PSC(port)->sicr, val);  in mpc52xx_psc_set_sicr()
431 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
432 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
433 	out_be32(&FIFO_512x(port)->txalarm, 1);  in mpc512x_psc_fifo_init()
434 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_fifo_init()
436 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
437 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
438 	out_be32(&FIFO_512x(port)->rxalarm, 1);  in mpc512x_psc_fifo_init()
439 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_fifo_init()
441 	out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
442 	out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
481 	out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);  in mpc512x_psc_stop_rx()
490 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_start_tx()
499 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_stop_tx()
504 	out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));  in mpc512x_psc_rx_clr_irq()
509 	out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));  in mpc512x_psc_tx_clr_irq()
527 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_cw_disable_ints()
528 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_cw_disable_ints()
533 	out_be32(&FIFO_512x(port)->tximr,  in mpc512x_psc_cw_restore_ints()
535 	out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);  in mpc512x_psc_cw_restore_ints()
775 	out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc5125_psc_fifo_init()
776 	out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc5125_psc_fifo_init()
777 	out_be32(&FIFO_5125(port)->txalarm, 1);  in mpc5125_psc_fifo_init()
778 	out_be32(&FIFO_5125(port)->tximr, 0);  in mpc5125_psc_fifo_init()
780 	out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc5125_psc_fifo_init()
781 	out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc5125_psc_fifo_init()
782 	out_be32(&FIFO_5125(port)->rxalarm, 1);  in mpc5125_psc_fifo_init()
783 	out_be32(&FIFO_5125(port)->rximr, 0);  in mpc5125_psc_fifo_init()
785 	out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);  in mpc5125_psc_fifo_init()
786 	out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);  in mpc5125_psc_fifo_init()
822 	out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);  in mpc5125_psc_stop_rx()
831 	out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);  in mpc5125_psc_start_tx()
840 	out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);  in mpc5125_psc_stop_tx()
845 	out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));  in mpc5125_psc_rx_clr_irq()
850 	out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));  in mpc5125_psc_tx_clr_irq()
868 	out_be32(&FIFO_5125(port)->tximr, 0);  in mpc5125_psc_cw_disable_ints()
869 	out_be32(&FIFO_5125(port)->rximr, 0);  in mpc5125_psc_cw_disable_ints()
874 	out_be32(&FIFO_5125(port)->tximr,  in mpc5125_psc_cw_restore_ints()
876 	out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);  in mpc5125_psc_cw_restore_ints()
958 	out_be32(&PSC_5125(port)->sicr, val);  in mpc5125_psc_set_sicr()