66 	return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?  in mcf_tx_empty()
77 	sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?  in mcf_get_mctrl()
95 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);  in mcf_set_mctrl()
97 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);  in mcf_set_mctrl()
108 		writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);  in mcf_start_tx()
110 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);  in mcf_start_tx()
113 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_start_tx()
123 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_stop_tx()
133 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_stop_rx()
144 		writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);  in mcf_break_ctl()
146 		writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);  in mcf_break_ctl()
160 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);  in mcf_startup()
161 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);  in mcf_startup()
165 		port->membase + MCFUART_UCR);  in mcf_startup()
169 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_startup()
187 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_shutdown()
190 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);  in mcf_shutdown()
191 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);  in mcf_shutdown()
266 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);  in mcf_set_termios()
267 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);  in mcf_set_termios()
268 	writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);  in mcf_set_termios()
269 	writeb(mr1, port->membase + MCFUART_UMR);  in mcf_set_termios()
270 	writeb(mr2, port->membase + MCFUART_UMR);  in mcf_set_termios()
271 	writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);  in mcf_set_termios()
272 	writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);  in mcf_set_termios()
274 	writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);  in mcf_set_termios()
277 		port->membase + MCFUART_UCSR);  in mcf_set_termios()
279 		port->membase + MCFUART_UCR);  in mcf_set_termios()
290 	while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {  in mcf_rx_chars()
291 		ch = readb(port->membase + MCFUART_URB);  in mcf_rx_chars()
297 				port->membase + MCFUART_UCR);  in mcf_rx_chars()
340 		writeb(port->x_char, port->membase + MCFUART_UTB);  in mcf_tx_chars()
346 	while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {  in mcf_tx_chars()
349 		writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);  in mcf_tx_chars()
359 		writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_tx_chars()
363 				port->membase + MCFUART_UCR);  in mcf_tx_chars()
376 	isr = readb(port->membase + MCFUART_UISR) & pp->imr;  in mcf_interrupt()
400 	writeb(0, port->membase + MCFUART_UIMR);  in mcf_config_port()
446 	mr1 = readb(port->membase + MCFUART_UMR);  in mcf_config_rs485()
447 	mr2 = readb(port->membase + MCFUART_UMR);  in mcf_config_rs485()
456 	writeb(mr1, port->membase + MCFUART_UMR);  in mcf_config_rs485()
457 	writeb(mr2, port->membase + MCFUART_UMR);  in mcf_config_rs485()
505 		port->membase = (platp[i].membase) ? platp[i].membase :  in early_mcf_setup()
526 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)  in mcf_console_putc()
529 	writeb(c, port->membase + MCFUART_UTB);  in mcf_console_putc()
531 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)  in mcf_console_putc()
560 	if (port->membase == 0)  in mcf_console_setup()
630 		port->membase = (platp[i].membase) ? platp[i].membase :  in mcf_probe()