Lines Matching refs:port
262 struct uart_port port; member
279 static u8 max310x_port_read(struct uart_port *port, u8 reg) in max310x_port_read() argument
281 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_read()
284 regmap_read(s->regmap, port->iobase + reg, &val); in max310x_port_read()
289 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) in max310x_port_write() argument
291 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_write()
293 regmap_write(s->regmap, port->iobase + reg, val); in max310x_port_write()
296 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) in max310x_port_update() argument
298 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_update()
300 regmap_update_bits(s->regmap, port->iobase + reg, mask, val); in max310x_port_update()
365 static void max310x_power(struct uart_port *port, int on) in max310x_power() argument
367 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_power()
396 static void max14830_power(struct uart_port *port, int on) in max14830_power() argument
398 max310x_port_update(port, MAX310X_BRGCFG_REG, in max14830_power()
487 static int max310x_set_baud(struct uart_port *port, int baud) in max310x_set_baud() argument
489 unsigned int mode = 0, clk = port->uartclk, div = clk / baud; in max310x_set_baud()
498 clk = port->uartclk * 2; in max310x_set_baud()
504 clk = port->uartclk * 4; in max310x_set_baud()
509 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); in max310x_set_baud()
510 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); in max310x_set_baud()
511 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); in max310x_set_baud()
592 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) in max310x_handle_rx() argument
596 if (unlikely(rxlen >= port->fifosize)) { in max310x_handle_rx()
597 dev_warn_ratelimited(port->dev, in max310x_handle_rx()
599 port->line); in max310x_handle_rx()
600 port->icount.buf_overrun++; in max310x_handle_rx()
602 rxlen = port->fifosize; in max310x_handle_rx()
606 ch = max310x_port_read(port, MAX310X_RHR_REG); in max310x_handle_rx()
607 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); in max310x_handle_rx()
612 port->icount.rx++; in max310x_handle_rx()
617 port->icount.brk++; in max310x_handle_rx()
618 if (uart_handle_break(port)) in max310x_handle_rx()
621 port->icount.parity++; in max310x_handle_rx()
623 port->icount.frame++; in max310x_handle_rx()
625 port->icount.overrun++; in max310x_handle_rx()
627 sts &= port->read_status_mask; in max310x_handle_rx()
638 if (uart_handle_sysrq_char(port, ch)) in max310x_handle_rx()
641 if (sts & port->ignore_status_mask) in max310x_handle_rx()
644 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); in max310x_handle_rx()
647 tty_flip_buffer_push(&port->state->port); in max310x_handle_rx()
650 static void max310x_handle_tx(struct uart_port *port) in max310x_handle_tx() argument
652 struct circ_buf *xmit = &port->state->xmit; in max310x_handle_tx()
655 if (unlikely(port->x_char)) { in max310x_handle_tx()
656 max310x_port_write(port, MAX310X_THR_REG, port->x_char); in max310x_handle_tx()
657 port->icount.tx++; in max310x_handle_tx()
658 port->x_char = 0; in max310x_handle_tx()
662 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) in max310x_handle_tx()
669 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); in max310x_handle_tx()
670 txlen = port->fifosize - txlen; in max310x_handle_tx()
674 port->icount.tx += to_send; in max310x_handle_tx()
676 max310x_port_write(port, MAX310X_THR_REG, in max310x_handle_tx()
683 uart_write_wakeup(port); in max310x_handle_tx()
688 struct uart_port *port = &s->p[portno].port; in max310x_port_irq() local
694 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); in max310x_port_irq()
695 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); in max310x_port_irq()
700 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); in max310x_port_irq()
701 uart_handle_cts_change(port, in max310x_port_irq()
705 max310x_handle_rx(port, rxlen); in max310x_port_irq()
708 max310x_handle_tx(port); in max310x_port_irq()
738 struct max310x_port *s = dev_get_drvdata(one->port.dev); in max310x_wq_proc()
741 max310x_handle_tx(&one->port); in max310x_wq_proc()
745 static void max310x_start_tx(struct uart_port *port) in max310x_start_tx() argument
747 struct max310x_one *one = container_of(port, struct max310x_one, port); in max310x_start_tx()
753 static unsigned int max310x_tx_empty(struct uart_port *port) in max310x_tx_empty() argument
757 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); in max310x_tx_empty()
758 sts = max310x_port_read(port, MAX310X_IRQSTS_REG); in max310x_tx_empty()
763 static unsigned int max310x_get_mctrl(struct uart_port *port) in max310x_get_mctrl() argument
775 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_md_proc()
777 (one->port.mctrl & TIOCM_LOOP) ? in max310x_md_proc()
781 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) in max310x_set_mctrl() argument
783 struct max310x_one *one = container_of(port, struct max310x_one, port); in max310x_set_mctrl()
788 static void max310x_break_ctl(struct uart_port *port, int break_state) in max310x_break_ctl() argument
790 max310x_port_update(port, MAX310X_LCR_REG, in max310x_break_ctl()
795 static void max310x_set_termios(struct uart_port *port, in max310x_set_termios() argument
834 max310x_port_write(port, MAX310X_LCR_REG, lcr); in max310x_set_termios()
837 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; in max310x_set_termios()
839 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
842 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
845 port->ignore_status_mask = 0; in max310x_set_termios()
847 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
849 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
855 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); in max310x_set_termios()
856 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); in max310x_set_termios()
866 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); in max310x_set_termios()
869 baud = uart_get_baud_rate(port, termios, old, in max310x_set_termios()
870 port->uartclk / 16 / 0xffff, in max310x_set_termios()
871 port->uartclk / 4); in max310x_set_termios()
874 baud = max310x_set_baud(port, baud); in max310x_set_termios()
877 uart_update_timeout(port, termios->c_cflag, baud); in max310x_set_termios()
880 static int max310x_rs485_config(struct uart_port *port, in max310x_rs485_config() argument
891 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); in max310x_rs485_config()
893 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_rs485_config()
896 max310x_port_update(port, MAX310X_MODE2_REG, in max310x_rs485_config()
900 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_rs485_config()
902 max310x_port_update(port, MAX310X_MODE2_REG, in max310x_rs485_config()
908 port->rs485 = *rs485; in max310x_rs485_config()
913 static int max310x_startup(struct uart_port *port) in max310x_startup() argument
915 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_startup()
918 s->devtype->power(port, 1); in max310x_startup()
921 max310x_port_update(port, MAX310X_MODE1_REG, in max310x_startup()
926 max310x_port_write(port, MAX310X_MODE2_REG, val); in max310x_startup()
927 max310x_port_update(port, MAX310X_MODE2_REG, in max310x_startup()
932 max310x_port_write(port, MAX310X_FLOWLVL_REG, in max310x_startup()
936 max310x_port_read(port, MAX310X_IRQSTS_REG); in max310x_startup()
940 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); in max310x_startup()
945 static void max310x_shutdown(struct uart_port *port) in max310x_shutdown() argument
947 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_shutdown()
950 max310x_port_write(port, MAX310X_IRQEN_REG, 0); in max310x_shutdown()
952 s->devtype->power(port, 0); in max310x_shutdown()
955 static const char *max310x_type(struct uart_port *port) in max310x_type() argument
957 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_type()
959 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; in max310x_type()
962 static int max310x_request_port(struct uart_port *port) in max310x_request_port() argument
968 static void max310x_config_port(struct uart_port *port, int flags) in max310x_config_port() argument
971 port->type = PORT_MAX310X; in max310x_config_port()
974 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) in max310x_verify_port() argument
978 if (s->irq != port->irq) in max310x_verify_port()
984 static void max310x_null_void(struct uart_port *port) in max310x_null_void() argument
1013 uart_suspend_port(&s->uart, &s->p[i].port); in max310x_suspend()
1014 s->devtype->power(&s->p[i].port, 0); in max310x_suspend()
1026 s->devtype->power(&s->p[i].port, 1); in max310x_resume()
1027 uart_resume_port(&s->uart, &s->p[i].port); in max310x_resume()
1040 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_get() local
1042 val = max310x_port_read(port, MAX310X_GPIODATA_REG); in max310x_gpio_get()
1050 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set() local
1052 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), in max310x_gpio_set()
1059 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_input() local
1061 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); in max310x_gpio_direction_input()
1070 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_output() local
1072 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), in max310x_gpio_direction_output()
1074 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), in max310x_gpio_direction_output()
1195 s->p[i].port.line = i; in max310x_probe()
1196 s->p[i].port.dev = dev; in max310x_probe()
1197 s->p[i].port.irq = irq; in max310x_probe()
1198 s->p[i].port.type = PORT_MAX310X; in max310x_probe()
1199 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; in max310x_probe()
1200 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; in max310x_probe()
1201 s->p[i].port.iotype = UPIO_PORT; in max310x_probe()
1202 s->p[i].port.iobase = i * 0x20; in max310x_probe()
1203 s->p[i].port.membase = (void __iomem *)~0; in max310x_probe()
1204 s->p[i].port.uartclk = uartclk; in max310x_probe()
1205 s->p[i].port.rs485_config = max310x_rs485_config; in max310x_probe()
1206 s->p[i].port.ops = &max310x_ops; in max310x_probe()
1208 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); in max310x_probe()
1210 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); in max310x_probe()
1212 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG, in max310x_probe()
1220 uart_add_one_port(&s->uart, &s->p[i].port); in max310x_probe()
1222 devtype->power(&s->p[i].port, 0); in max310x_probe()
1260 uart_remove_one_port(&s->uart, &s->p[i].port); in max310x_remove()
1261 s->devtype->power(&s->p[i].port, 0); in max310x_remove()