Lines Matching refs:ch
61 static void cls_set_cts_flow_control(struct jsm_channel *ch) in cls_set_cts_flow_control() argument
63 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
64 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
71 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
73 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
79 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
82 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
90 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
93 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
97 &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
99 ch->ch_t_tlevel = 16; in cls_set_cts_flow_control()
102 static void cls_set_ixon_flow_control(struct jsm_channel *ch) in cls_set_ixon_flow_control() argument
104 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
105 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
112 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
114 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
120 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
123 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixon_flow_control()
124 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixon_flow_control()
125 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixon_flow_control()
126 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixon_flow_control()
129 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
137 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
140 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
144 &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
147 static void cls_set_no_output_flow_control(struct jsm_channel *ch) in cls_set_no_output_flow_control() argument
149 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
150 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
157 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
159 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
165 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
168 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
176 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
179 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
183 &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
185 ch->ch_r_watermark = 0; in cls_set_no_output_flow_control()
186 ch->ch_t_tlevel = 16; in cls_set_no_output_flow_control()
187 ch->ch_r_tlevel = 16; in cls_set_no_output_flow_control()
190 static void cls_set_rts_flow_control(struct jsm_channel *ch) in cls_set_rts_flow_control() argument
192 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
193 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
200 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
202 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
208 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
211 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
215 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
218 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
222 &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
224 ch->ch_r_watermark = 4; in cls_set_rts_flow_control()
225 ch->ch_r_tlevel = 8; in cls_set_rts_flow_control()
228 static void cls_set_ixoff_flow_control(struct jsm_channel *ch) in cls_set_ixoff_flow_control() argument
230 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
231 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
238 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
240 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
246 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
249 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixoff_flow_control()
250 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixoff_flow_control()
251 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixoff_flow_control()
252 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixoff_flow_control()
255 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
259 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
262 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
266 &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
269 static void cls_set_no_input_flow_control(struct jsm_channel *ch) in cls_set_no_input_flow_control() argument
271 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
272 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
279 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
281 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
287 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
290 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
294 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
297 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
301 &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
303 ch->ch_t_tlevel = 16; in cls_set_no_input_flow_control()
304 ch->ch_r_tlevel = 16; in cls_set_no_input_flow_control()
314 static void cls_clear_break(struct jsm_channel *ch) in cls_clear_break() argument
318 spin_lock_irqsave(&ch->ch_lock, lock_flags); in cls_clear_break()
321 if (ch->ch_flags & CH_BREAK_SENDING) { in cls_clear_break()
322 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_clear_break()
324 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_clear_break()
326 ch->ch_flags &= ~(CH_BREAK_SENDING); in cls_clear_break()
327 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in cls_clear_break()
331 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in cls_clear_break()
334 static void cls_disable_receiver(struct jsm_channel *ch) in cls_disable_receiver() argument
336 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_disable_receiver()
339 writeb(tmp, &ch->ch_cls_uart->ier); in cls_disable_receiver()
342 static void cls_enable_receiver(struct jsm_channel *ch) in cls_enable_receiver() argument
344 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_enable_receiver()
347 writeb(tmp, &ch->ch_cls_uart->ier); in cls_enable_receiver()
351 static void cls_assert_modem_signals(struct jsm_channel *ch) in cls_assert_modem_signals() argument
353 if (!ch) in cls_assert_modem_signals()
356 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); in cls_assert_modem_signals()
359 static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch) in cls_copy_data_from_uart_to_queue() argument
368 if (!ch) in cls_copy_data_from_uart_to_queue()
371 spin_lock_irqsave(&ch->ch_lock, flags); in cls_copy_data_from_uart_to_queue()
374 head = ch->ch_r_head & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
375 tail = ch->ch_r_tail & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
378 linestatus = ch->ch_cached_lsr; in cls_copy_data_from_uart_to_queue()
379 ch->ch_cached_lsr = 0; in cls_copy_data_from_uart_to_queue()
390 if (ch->ch_c_iflag & IGNBRK) in cls_copy_data_from_uart_to_queue()
398 linestatus = readb(&ch->ch_cls_uart->lsr); in cls_copy_data_from_uart_to_queue()
412 discard = readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
426 ch->ch_r_tail = tail; in cls_copy_data_from_uart_to_queue()
427 ch->ch_err_overrun++; in cls_copy_data_from_uart_to_queue()
431 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE in cls_copy_data_from_uart_to_queue()
433 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
437 if (ch->ch_equeue[head] & UART_LSR_PE) in cls_copy_data_from_uart_to_queue()
438 ch->ch_err_parity++; in cls_copy_data_from_uart_to_queue()
439 if (ch->ch_equeue[head] & UART_LSR_BI) in cls_copy_data_from_uart_to_queue()
440 ch->ch_err_break++; in cls_copy_data_from_uart_to_queue()
441 if (ch->ch_equeue[head] & UART_LSR_FE) in cls_copy_data_from_uart_to_queue()
442 ch->ch_err_frame++; in cls_copy_data_from_uart_to_queue()
446 ch->ch_rxcount++; in cls_copy_data_from_uart_to_queue()
452 ch->ch_r_head = head & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
453 ch->ch_e_head = head & EQUEUEMASK; in cls_copy_data_from_uart_to_queue()
455 spin_unlock_irqrestore(&ch->ch_lock, flags); in cls_copy_data_from_uart_to_queue()
458 static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch) in cls_copy_data_from_queue_to_uart() argument
466 if (!ch) in cls_copy_data_from_queue_to_uart()
469 circ = &ch->uart_port.state->xmit; in cls_copy_data_from_queue_to_uart()
476 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) in cls_copy_data_from_queue_to_uart()
480 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) in cls_copy_data_from_queue_to_uart()
493 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx); in cls_copy_data_from_queue_to_uart()
496 ch->ch_txcount++; in cls_copy_data_from_queue_to_uart()
503 if (len_written > ch->ch_t_tlevel) in cls_copy_data_from_queue_to_uart()
504 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_copy_data_from_queue_to_uart()
507 uart_write_wakeup(&ch->uart_port); in cls_copy_data_from_queue_to_uart()
510 static void cls_parse_modem(struct jsm_channel *ch, u8 signals) in cls_parse_modem() argument
514 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in cls_parse_modem()
516 ch->ch_portnum, msignals); in cls_parse_modem()
526 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); in cls_parse_modem()
528 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS); in cls_parse_modem()
531 ch->ch_mistat |= UART_MSR_DCD; in cls_parse_modem()
533 ch->ch_mistat &= ~UART_MSR_DCD; in cls_parse_modem()
536 ch->ch_mistat |= UART_MSR_DSR; in cls_parse_modem()
538 ch->ch_mistat &= ~UART_MSR_DSR; in cls_parse_modem()
541 ch->ch_mistat |= UART_MSR_RI; in cls_parse_modem()
543 ch->ch_mistat &= ~UART_MSR_RI; in cls_parse_modem()
546 ch->ch_mistat |= UART_MSR_CTS; in cls_parse_modem()
548 ch->ch_mistat &= ~UART_MSR_CTS; in cls_parse_modem()
550 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in cls_parse_modem()
552 ch->ch_portnum, in cls_parse_modem()
553 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), in cls_parse_modem()
554 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), in cls_parse_modem()
555 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), in cls_parse_modem()
556 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), in cls_parse_modem()
557 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), in cls_parse_modem()
558 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); in cls_parse_modem()
564 struct jsm_channel *ch; in cls_parse_isr() local
576 ch = brd->channels[port]; in cls_parse_isr()
577 if (!ch) in cls_parse_isr()
582 isr = readb(&ch->ch_cls_uart->isr_fcr); in cls_parse_isr()
591 cls_copy_data_from_uart_to_queue(ch); in cls_parse_isr()
592 jsm_check_queue_flow_control(ch); in cls_parse_isr()
598 spin_lock_irqsave(&ch->ch_lock, flags); in cls_parse_isr()
599 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_parse_isr()
600 spin_unlock_irqrestore(&ch->ch_lock, flags); in cls_parse_isr()
601 cls_copy_data_from_queue_to_uart(ch); in cls_parse_isr()
611 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_parse_isr()
616 static void cls_flush_uart_write(struct jsm_channel *ch) in cls_flush_uart_write() argument
621 if (!ch) in cls_flush_uart_write()
625 &ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
629 tmp = readb(&ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
631 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in cls_flush_uart_write()
638 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_flush_uart_write()
642 static void cls_flush_uart_read(struct jsm_channel *ch) in cls_flush_uart_read() argument
644 if (!ch) in cls_flush_uart_read()
661 static void cls_send_start_character(struct jsm_channel *ch) in cls_send_start_character() argument
663 if (!ch) in cls_send_start_character()
666 if (ch->ch_startc != __DISABLED_CHAR) { in cls_send_start_character()
667 ch->ch_xon_sends++; in cls_send_start_character()
668 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); in cls_send_start_character()
672 static void cls_send_stop_character(struct jsm_channel *ch) in cls_send_stop_character() argument
674 if (!ch) in cls_send_stop_character()
677 if (ch->ch_stopc != __DISABLED_CHAR) { in cls_send_stop_character()
678 ch->ch_xoff_sends++; in cls_send_stop_character()
679 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); in cls_send_stop_character()
687 static void cls_param(struct jsm_channel *ch) in cls_param() argument
698 bd = ch->ch_bd; in cls_param()
705 if ((ch->ch_c_cflag & (CBAUD)) == 0) { in cls_param()
706 ch->ch_r_head = 0; in cls_param()
707 ch->ch_r_tail = 0; in cls_param()
708 ch->ch_e_head = 0; in cls_param()
709 ch->ch_e_tail = 0; in cls_param()
711 cls_flush_uart_write(ch); in cls_param()
712 cls_flush_uart_read(ch); in cls_param()
715 ch->ch_flags |= (CH_BAUD0); in cls_param()
716 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); in cls_param()
717 cls_assert_modem_signals(ch); in cls_param()
721 cflag = C_BAUD(ch->uart_port.state->port.tty); in cls_param()
730 if (ch->ch_flags & CH_BAUD0) in cls_param()
731 ch->ch_flags &= ~(CH_BAUD0); in cls_param()
733 if (ch->ch_c_cflag & PARENB) in cls_param()
736 if (!(ch->ch_c_cflag & PARODD)) in cls_param()
744 if (ch->ch_c_cflag & CMSPAR) in cls_param()
748 if (ch->ch_c_cflag & CSTOPB) in cls_param()
751 switch (ch->ch_c_cflag & CSIZE) { in cls_param()
767 ier = readb(&ch->ch_cls_uart->ier); in cls_param()
768 uart_lcr = readb(&ch->ch_cls_uart->lcr); in cls_param()
770 quot = ch->ch_bd->bd_dividend / baud; in cls_param()
773 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); in cls_param()
774 writeb((quot & 0xff), &ch->ch_cls_uart->txrx); in cls_param()
775 writeb((quot >> 8), &ch->ch_cls_uart->ier); in cls_param()
776 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
780 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
782 if (ch->ch_c_cflag & CREAD) in cls_param()
787 writeb(ier, &ch->ch_cls_uart->ier); in cls_param()
789 if (ch->ch_c_cflag & CRTSCTS) in cls_param()
790 cls_set_cts_flow_control(ch); in cls_param()
791 else if (ch->ch_c_iflag & IXON) { in cls_param()
796 if ((ch->ch_startc == __DISABLED_CHAR) || in cls_param()
797 (ch->ch_stopc == __DISABLED_CHAR)) in cls_param()
798 cls_set_no_output_flow_control(ch); in cls_param()
800 cls_set_ixon_flow_control(ch); in cls_param()
802 cls_set_no_output_flow_control(ch); in cls_param()
804 if (ch->ch_c_cflag & CRTSCTS) in cls_param()
805 cls_set_rts_flow_control(ch); in cls_param()
806 else if (ch->ch_c_iflag & IXOFF) { in cls_param()
811 if ((ch->ch_startc == __DISABLED_CHAR) || in cls_param()
812 (ch->ch_stopc == __DISABLED_CHAR)) in cls_param()
813 cls_set_no_input_flow_control(ch); in cls_param()
815 cls_set_ixoff_flow_control(ch); in cls_param()
817 cls_set_no_input_flow_control(ch); in cls_param()
819 cls_assert_modem_signals(ch); in cls_param()
822 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_param()
868 static void cls_uart_init(struct jsm_channel *ch) in cls_uart_init() argument
870 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); in cls_uart_init()
873 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_init()
879 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_uart_init()
881 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_uart_init()
886 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
889 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_uart_init()
892 readb(&ch->ch_cls_uart->txrx); in cls_uart_init()
895 &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
898 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_uart_init()
900 readb(&ch->ch_cls_uart->lsr); in cls_uart_init()
901 readb(&ch->ch_cls_uart->msr); in cls_uart_init()
907 static void cls_uart_off(struct jsm_channel *ch) in cls_uart_off() argument
910 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_off()
919 static u32 cls_get_uart_bytes_left(struct jsm_channel *ch) in cls_get_uart_bytes_left() argument
922 u8 lsr = readb(&ch->ch_cls_uart->lsr); in cls_get_uart_bytes_left()
928 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_get_uart_bytes_left()
941 static void cls_send_break(struct jsm_channel *ch) in cls_send_break() argument
944 if (!(ch->ch_flags & CH_BREAK_SENDING)) { in cls_send_break()
945 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_send_break()
947 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_send_break()
948 ch->ch_flags |= (CH_BREAK_SENDING); in cls_send_break()
959 static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c) in cls_send_immediate_char() argument
961 writeb(c, &ch->ch_cls_uart->txrx); in cls_send_immediate_char()