50 #define UCR1  0x80 /* Control Register 1 */  macro
293 	ucr->ucr1 = readl(port->membase + UCR1);  in imx_port_ucrs_save()
302 	writel(ucr->ucr1, port->membase + UCR1);  in imx_port_ucrs_restore()
368 	temp = readl(port->membase + UCR1);  in imx_stop_tx()
369 	writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);  in imx_stop_tx()
408 	temp = readl(sport->port.membase + UCR1);  in imx_stop_rx()
409 	writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);  in imx_stop_rx()
446 		temp = readl(sport->port.membase + UCR1);  in imx_transmit_buffer()
450 			writel(temp, sport->port.membase + UCR1);  in imx_transmit_buffer()
452 			writel(temp, sport->port.membase + UCR1);  in imx_transmit_buffer()
485 	temp = readl(sport->port.membase + UCR1);  in dma_tx_callback()
487 	writel(temp, sport->port.membase + UCR1);  in dma_tx_callback()
559 	temp = readl(sport->port.membase + UCR1);  in imx_dma_tx()
561 	writel(temp, sport->port.membase + UCR1);  in imx_dma_tx()
593 		temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
594 		writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);  in imx_start_tx()
601 			temp = readl(sport->port.membase + UCR1);  in imx_start_tx()
604 			writel(temp, sport->port.membase + UCR1);  in imx_start_tx()
729 		temp = readl(sport->port.membase + UCR1);  in imx_dma_rxint()
731 		writel(temp, sport->port.membase + UCR1);  in imx_dma_rxint()
757 	     readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||  in imx_int()
843 	temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;  in imx_break_ctl()
848 	writel(temp, sport->port.membase + UCR1);  in imx_break_ctl()
876 	temp = readl(sport->port.membase + UCR1);  in imx_rx_dma_done()
878 	writel(temp, sport->port.membase + UCR1);  in imx_rx_dma_done()
1058 	temp = readl(sport->port.membase + UCR1);  in imx_enable_dma()
1062 	writel(temp, sport->port.membase + UCR1);  in imx_enable_dma()
1077 	temp = readl(sport->port.membase + UCR1);  in imx_disable_dma()
1079 	writel(temp, sport->port.membase + UCR1);  in imx_disable_dma()
1143 	temp = readl(sport->port.membase + UCR1);  in imx_startup()
1146 	writel(temp, sport->port.membase + UCR1);  in imx_startup()
1215 	temp = readl(sport->port.membase + UCR1);  in imx_shutdown()
1218 	writel(temp, sport->port.membase + UCR1);  in imx_shutdown()
1240 		temp = readl(sport->port.membase + UCR1);  in imx_flush_buffer()
1242 		writel(temp, sport->port.membase + UCR1);  in imx_flush_buffer()
1377 	old_ucr1 = readl(sport->port.membase + UCR1);  in imx_set_termios()
1379 			sport->port.membase + UCR1);  in imx_set_termios()
1426 	writel(old_ucr1, sport->port.membase + UCR1);  in imx_set_termios()
1505 	temp = readl(sport->port.membase + UCR1);  in imx_poll_init()
1510 	writel(temp, sport->port.membase + UCR1);  in imx_poll_init()
1656 	writel(ucr1, sport->port.membase + UCR1);  in imx_console_write()
1686 	if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {  in imx_console_get_options()