Lines Matching refs:membase
289 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
291 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
298 temp = lpuart32_read(port->membase + UARTCTRL); in lpuart32_stop_tx()
300 lpuart32_write(temp, port->membase + UARTCTRL); in lpuart32_stop_tx()
307 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
315 temp = lpuart32_read(port->membase + UARTCTRL); in lpuart32_stop_rx()
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL); in lpuart32_stop_rx()
353 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) { in lpuart_pio_tx()
354 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); in lpuart_pio_tx()
363 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS, in lpuart_pio_tx()
364 sport->port.membase + UARTCR5); in lpuart_pio_tx()
406 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS, in lpuart_prepare_tx()
407 sport->port.membase + UARTCR5); in lpuart_prepare_tx()
409 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS, in lpuart_prepare_tx()
410 sport->port.membase + UARTCR5); in lpuart_prepare_tx()
507 temp = readb(sport->port.membase + UARTCR5); in lpuart_timer_func()
508 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_timer_func()
524 temp = readb(sport->port.membase + UARTCR5); in lpuart_prepare_rx()
525 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_prepare_rx()
535 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { in lpuart_transmit_buffer()
536 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); in lpuart_transmit_buffer()
553 txcnt = lpuart32_read(sport->port.membase + UARTWATER); in lpuart32_transmit_buffer()
557 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA); in lpuart32_transmit_buffer()
560 txcnt = lpuart32_read(sport->port.membase + UARTWATER); in lpuart32_transmit_buffer()
579 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
580 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
586 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
596 temp = lpuart32_read(port->membase + UARTCTRL); in lpuart32_start_tx()
597 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL); in lpuart32_start_tx()
599 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE) in lpuart32_start_tx()
612 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA); in lpuart_txint()
614 writeb(sport->port.x_char, sport->port.membase + UARTDR); in lpuart_txint()
649 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
656 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
657 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
712 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
719 sr = lpuart32_read(sport->port.membase + UARTSTAT); in lpuart32_rxint()
720 rx = lpuart32_read(sport->port.membase + UARTDATA); in lpuart32_rxint()
771 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
772 crdma = readb(sport->port.membase + UARTCR5); in lpuart_int()
795 sts = lpuart32_read(sport->port.membase + UARTSTAT); in lpuart32_int()
796 rxcount = lpuart32_read(sport->port.membase + UARTWATER); in lpuart32_int()
803 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE)) in lpuart32_int()
806 lpuart32_write(sts, sport->port.membase + UARTSTAT); in lpuart32_int()
813 return (readb(port->membase + UARTSR1) & UARTSR1_TC) ? in lpuart_tx_empty()
819 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ? in lpuart32_tx_empty()
828 reg = readb(port->membase + UARTMODEM); in lpuart_get_mctrl()
843 reg = lpuart32_read(port->membase + UARTMODIR); in lpuart32_get_mctrl()
857 temp = readb(port->membase + UARTMODEM) & in lpuart_set_mctrl()
866 writeb(temp, port->membase + UARTMODEM); in lpuart_set_mctrl()
873 temp = lpuart32_read(port->membase + UARTMODIR) & in lpuart32_set_mctrl()
882 lpuart32_write(temp, port->membase + UARTMODIR); in lpuart32_set_mctrl()
889 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
894 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
901 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK; in lpuart32_break_ctl()
906 lpuart32_write(temp, port->membase + UARTCTRL); in lpuart32_break_ctl()
914 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
918 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
920 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
922 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
925 readb(sport->port.membase + UARTSR1); in lpuart_setup_watermark()
929 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
931 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
932 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
935 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
943 ctrl = lpuart32_read(sport->port.membase + UARTCTRL); in lpuart32_setup_watermark()
947 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); in lpuart32_setup_watermark()
950 val = lpuart32_read(sport->port.membase + UARTFIFO); in lpuart32_setup_watermark()
953 lpuart32_write(val, sport->port.membase + UARTFIFO); in lpuart32_setup_watermark()
957 lpuart32_write(val, sport->port.membase + UARTWATER); in lpuart32_setup_watermark()
960 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL); in lpuart32_setup_watermark()
1077 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1097 temp = readb(port->membase + UARTCR5); in lpuart_startup()
1099 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); in lpuart_startup()
1112 temp = readb(sport->port.membase + UARTCR2); in lpuart_startup()
1114 writeb(temp, sport->port.membase + UARTCR2); in lpuart_startup()
1128 temp = lpuart32_read(sport->port.membase + UARTFIFO); in lpuart32_startup()
1145 temp = lpuart32_read(sport->port.membase + UARTCTRL); in lpuart32_startup()
1148 lpuart32_write(temp, sport->port.membase + UARTCTRL); in lpuart32_startup()
1163 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1166 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1190 temp = lpuart32_read(port->membase + UARTCTRL); in lpuart32_shutdown()
1193 lpuart32_write(temp, port->membase + UARTCTRL); in lpuart32_shutdown()
1211 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1212 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1213 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1214 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1215 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1312 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) in lpuart_set_termios()
1317 sport->port.membase + UARTCR2); in lpuart_set_termios()
1325 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
1326 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
1327 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
1328 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
1329 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
1332 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
1348 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL); in lpuart32_set_termios()
1349 bd = lpuart32_read(sport->port.membase + UARTBAUD); in lpuart32_set_termios()
1350 modem = lpuart32_read(sport->port.membase + UARTMODIR); in lpuart32_set_termios()
1436 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) in lpuart32_set_termios()
1441 sport->port.membase + UARTCTRL); in lpuart32_set_termios()
1448 lpuart32_write(bd, sport->port.membase + UARTBAUD); in lpuart32_set_termios()
1449 lpuart32_write(modem, sport->port.membase + UARTMODIR); in lpuart32_set_termios()
1450 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); in lpuart32_set_termios()
1540 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) in lpuart_console_putchar()
1543 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
1548 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)) in lpuart32_console_putchar()
1551 lpuart32_write(ch, port->membase + UARTDATA); in lpuart32_console_putchar()
1561 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
1564 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
1569 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) in lpuart_console_write()
1572 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
1582 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL); in lpuart32_console_write()
1585 lpuart32_write(cr, sport->port.membase + UARTCTRL); in lpuart32_console_write()
1590 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) in lpuart32_console_write()
1593 lpuart32_write(old_cr, sport->port.membase + UARTCTRL); in lpuart32_console_write()
1607 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
1614 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
1629 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
1631 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
1635 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
1656 cr = lpuart32_read(sport->port.membase + UARTCTRL); in lpuart32_console_get_options()
1663 cr = lpuart32_read(sport->port.membase + UARTCTRL); in lpuart32_console_get_options()
1678 bd = lpuart32_read(sport->port.membase + UARTBAUD); in lpuart32_console_get_options()
1786 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); in lpuart_probe()
1787 if (IS_ERR(sport->port.membase)) in lpuart_probe()
1788 return PTR_ERR(sport->port.membase); in lpuart_probe()
1869 temp = lpuart32_read(sport->port.membase + UARTCTRL); in lpuart_suspend()
1871 lpuart32_write(temp, sport->port.membase + UARTCTRL); in lpuart_suspend()
1874 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
1876 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
1891 temp = lpuart32_read(sport->port.membase + UARTCTRL); in lpuart_resume()
1894 lpuart32_write(temp, sport->port.membase + UARTCTRL); in lpuart_resume()
1897 temp = readb(sport->port.membase + UARTCR2); in lpuart_resume()
1899 writeb(temp, sport->port.membase + UARTCR2); in lpuart_resume()