428 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_callback()
542 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_refill()
578 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_irq()
580 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_tx_irq()
590 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_tx_irq()
604 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_stop()
630 				writew(uap->im, uap->port.membase +  in pl011_dma_tx_start()
636 			writew(uap->dmacr,  in pl011_dma_tx_start()
648 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_start()
659 	writew(uap->port.x_char, uap->port.membase + UART01x_DR);  in pl011_dma_tx_start()
665 	writew(dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_start()
693 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_flush_buffer()
733 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_trigger_dma()
737 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_rx_trigger_dma()
795 		writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,  in pl011_dma_rx_chars()
844 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_irq()
864 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_rx_irq()
912 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_rx_callback()
925 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_stop()
969 		writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_dma_rx_poll()
1031 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_startup()
1039 		writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,  in pl011_dma_startup()
1070 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_shutdown()
1171 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_stop_tx()
1181 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_start_tx_pio()
1202 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_stop_rx()
1213 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_enable_ms()
1233 			writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_rx_chars()
1261 	writew(c, uap->port.membase + UART01x_DR);  in pl011_tx_char()
1393 				writew(0x00, uap->port.membase + UART011_ICR);  in pl011_int()
1404 			writew(status & ~(UART011_TXIS|UART011_RTIS|  in pl011_int()
1488 	writew(cr, uap->port.membase + UART011_CR);  in pl011_set_mctrl()
1504 	writew(lcr_h, uap->port.membase + uap->lcrh_tx);  in pl011_break_ctl()
1516 	writew(readw(regs + UART011_MIS), regs + UART011_ICR);  in pl011_quiesce_irqs()
1530 	writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);  in pl011_quiesce_irqs()
1561 	writew(ch, uap->port.membase + UART01x_DR);  in pl011_put_poll_char()
1585 	writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |  in pl011_hwinit()
1593 	writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);  in pl011_hwinit()
1607 	writew(lcr_h, uap->port.membase + uap->lcrh_rx);  in pl011_write_lcr_h()
1615 			writew(0xff, uap->port.membase + UART011_MIS);  in pl011_write_lcr_h()
1616 		writew(lcr_h, uap->port.membase + uap->lcrh_tx);  in pl011_write_lcr_h()
1631 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_startup()
1640 	writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);  in pl011_startup()
1650 	writew(cr, uap->port.membase + UART011_CR);  in pl011_startup()
1669 	 writew(UART011_RTIS | UART011_RXIS,  in pl011_startup()
1674 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_startup()
1691       writew(val, uap->port.membase + lcrh);  in pl011_shutdown_channel()
1707 	writew(uap->im, uap->port.membase + UART011_IMSC);  in pl011_shutdown()
1708 	writew(0xffff, uap->port.membase + UART011_ICR);  in pl011_shutdown()
1730 	writew(cr, uap->port.membase + UART011_CR);  in pl011_shutdown()
1856 	writew(0, port->membase + UART011_CR);  in pl011_set_termios()
1889 	writew(quot & 0x3f, port->membase + UART011_FBRD);  in pl011_set_termios()
1890 	writew(quot >> 6, port->membase + UART011_IBRD);  in pl011_set_termios()
1899 	writew(old_cr, port->membase + UART011_CR);  in pl011_set_termios()
1990 	writew(ch, uap->port.membase + UART01x_DR);  in pl011_console_putchar()
2017 	writew(new_cr, uap->port.membase + UART011_CR);  in pl011_console_write()
2028 	writew(old_cr, uap->port.membase + UART011_CR);  in pl011_console_write()
2251 	writew(0, uap->port.membase + UART011_IMSC);  in pl011_probe()
2252 	writew(0xffff, uap->port.membase + UART011_ICR);  in pl011_probe()