186 		status = readw(uap->port.membase + UART01x_FR);  in pl011_fifo_to_tty()
191 		ch = readw(uap->port.membase + UART01x_DR) |  in pl011_fifo_to_tty()
650 	if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {  in pl011_dma_tx_start()
1065 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)  in pl011_dma_shutdown()
1258 	if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)  in pl011_tx_char()
1294 		     readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF))  in pl011_tx_chars()
1337 	status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl011_modem_status()
1388 	status = readw(uap->port.membase + UART011_MIS);  in pl011_int()
1400 				dummy_read = readw(uap->port.membase + UART011_ICR);  in pl011_int()
1401 				dummy_read = readw(uap->port.membase + UART011_ICR);  in pl011_int()
1425 			status = readw(uap->port.membase + UART011_MIS);  in pl011_int()
1439 	unsigned int status = readw(uap->port.membase + UART01x_FR);  in pl011_tx_empty()
1448 	unsigned int status = readw(uap->port.membase + UART01x_FR);  in pl011_get_mctrl()
1468 	cr = readw(uap->port.membase + UART011_CR);  in pl011_set_mctrl()
1499 	lcr_h = readw(uap->port.membase + uap->lcrh_tx);  in pl011_break_ctl()
1516 	writew(readw(regs + UART011_MIS), regs + UART011_ICR);  in pl011_quiesce_irqs()
1530 	writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);  in pl011_quiesce_irqs()
1545 	status = readw(uap->port.membase + UART01x_FR);  in pl011_get_poll_char()
1549 	return readw(uap->port.membase + UART01x_DR);  in pl011_get_poll_char()
1558 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)  in pl011_put_poll_char()
1592 	uap->im = readw(uap->port.membase + UART011_IMSC);  in pl011_hwinit()
1657 	uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl011_startup()
1689       val = readw(uap->port.membase + lcrh);  in pl011_shutdown_channel()
1726 	cr = readw(uap->port.membase + UART011_CR);  in pl011_shutdown()
1855 	old_cr = readw(port->membase + UART011_CR);  in pl011_set_termios()
1988 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)  in pl011_console_putchar()
2014 	old_cr = readw(uap->port.membase + UART011_CR);  in pl011_console_write()
2026 		status = readw(uap->port.membase + UART01x_FR);  in pl011_console_write()
2041 	if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {  in pl011_console_get_options()
2044 		lcr_h = readw(uap->port.membase + uap->lcrh_tx);  in pl011_console_get_options()
2059 		ibrd = readw(uap->port.membase + UART011_IBRD);  in pl011_console_get_options()
2060 		fbrd = readw(uap->port.membase + UART011_FBRD);  in pl011_console_get_options()
2065 			if (readw(uap->port.membase + UART011_CR)  in pl011_console_get_options()