Lines Matching refs:port
150 struct uart_port port; member
186 status = readw(uap->port.membase + UART01x_FR); in pl011_fifo_to_tty()
191 ch = readw(uap->port.membase + UART01x_DR) | in pl011_fifo_to_tty()
194 uap->port.icount.rx++; in pl011_fifo_to_tty()
200 uap->port.icount.brk++; in pl011_fifo_to_tty()
201 if (uart_handle_break(&uap->port)) in pl011_fifo_to_tty()
204 uap->port.icount.parity++; in pl011_fifo_to_tty()
206 uap->port.icount.frame++; in pl011_fifo_to_tty()
208 uap->port.icount.overrun++; in pl011_fifo_to_tty()
210 ch &= uap->port.read_status_mask; in pl011_fifo_to_tty()
220 if (uart_handle_sysrq_char(&uap->port, ch & 255)) in pl011_fifo_to_tty()
223 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); in pl011_fifo_to_tty()
271 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); in pl011_dma_probe()
272 struct device *dev = uap->port.dev; in pl011_dma_probe()
274 .dst_addr = uap->port.mapbase + UART01x_DR, in pl011_dma_probe()
293 dev_info(uap->port.dev, "no DMA platform data\n"); in pl011_dma_probe()
304 dev_err(uap->port.dev, "no TX DMA channel!\n"); in pl011_dma_probe()
312 dev_info(uap->port.dev, "DMA channel TX %s\n", in pl011_dma_probe()
322 dev_err(uap->port.dev, "no RX DMA channel!\n"); in pl011_dma_probe()
329 .src_addr = uap->port.mapbase + UART01x_DR, in pl011_dma_probe()
346 dev_info(uap->port.dev, in pl011_dma_probe()
393 dev_info(uap->port.dev, "DMA channel RX %s\n", in pl011_dma_probe()
421 spin_lock_irqsave(&uap->port.lock, flags); in pl011_dma_tx_callback()
428 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_callback()
439 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
440 uart_circ_empty(&uap->port.state->xmit)) { in pl011_dma_tx_callback()
442 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_tx_callback()
453 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_tx_callback()
470 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_dma_tx_refill()
514 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); in pl011_dma_tx_refill()
527 dev_dbg(uap->port.dev, "TX DMA busy\n"); in pl011_dma_tx_refill()
542 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_refill()
550 uap->port.icount.tx += count; in pl011_dma_tx_refill()
553 uart_write_wakeup(&uap->port); in pl011_dma_tx_refill()
578 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_irq()
580 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
590 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
604 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_stop()
623 if (!uap->port.x_char) { in pl011_dma_tx_start()
630 writew(uap->im, uap->port.membase + in pl011_dma_tx_start()
637 uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
648 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
650 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { in pl011_dma_tx_start()
659 writew(uap->port.x_char, uap->port.membase + UART01x_DR); in pl011_dma_tx_start()
660 uap->port.icount.tx++; in pl011_dma_tx_start()
661 uap->port.x_char = 0; in pl011_dma_tx_start()
665 writew(dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
674 static void pl011_dma_flush_buffer(struct uart_port *port) in pl011_dma_flush_buffer() argument
675 __releases(&uap->port.lock) in pl011_dma_flush_buffer()
676 __acquires(&uap->port.lock) in pl011_dma_flush_buffer()
679 container_of(port, struct uart_amba_port, port); in pl011_dma_flush_buffer()
685 spin_unlock(&uap->port.lock); in pl011_dma_flush_buffer()
687 spin_lock(&uap->port.lock); in pl011_dma_flush_buffer()
693 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_flush_buffer()
733 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_trigger_dma()
737 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_trigger_dma()
751 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_chars() local
776 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, in pl011_dma_rx_chars()
779 uap->port.icount.rx += dma_count; in pl011_dma_rx_chars()
781 dev_warn(uap->port.dev, in pl011_dma_rx_chars()
796 uap->port.membase + UART011_ICR); in pl011_dma_rx_chars()
812 spin_unlock(&uap->port.lock); in pl011_dma_rx_chars()
813 dev_vdbg(uap->port.dev, in pl011_dma_rx_chars()
816 tty_flip_buffer_push(port); in pl011_dma_rx_chars()
817 spin_lock(&uap->port.lock); in pl011_dma_rx_chars()
836 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
840 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
844 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_irq()
861 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_irq()
864 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_irq()
887 spin_lock_irq(&uap->port.lock); in pl011_dma_rx_callback()
903 spin_unlock_irq(&uap->port.lock); in pl011_dma_rx_callback()
909 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_callback()
912 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_callback()
925 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_stop()
936 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_poll() local
951 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, in pl011_dma_rx_poll()
957 tty_flip_buffer_push(port); in pl011_dma_rx_poll()
966 spin_lock_irqsave(&uap->port.lock, flags); in pl011_dma_rx_poll()
969 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_poll()
970 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_dma_rx_poll()
993 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); in pl011_dma_startup()
994 uap->port.fifosize = uap->fifosize; in pl011_dma_startup()
1001 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1011 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1019 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1031 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_startup()
1040 uap->port.membase + ST_UART011_DMAWM); in pl011_dma_startup()
1044 dev_dbg(uap->port.dev, "could not trigger initial " in pl011_dma_startup()
1065 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_dma_shutdown()
1068 spin_lock_irq(&uap->port.lock); in pl011_dma_shutdown()
1070 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_shutdown()
1071 spin_unlock_irq(&uap->port.lock); in pl011_dma_shutdown()
1165 static void pl011_stop_tx(struct uart_port *port) in pl011_stop_tx() argument
1168 container_of(port, struct uart_amba_port, port); in pl011_stop_tx()
1171 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_stop_tx()
1181 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_start_tx_pio()
1186 static void pl011_start_tx(struct uart_port *port) in pl011_start_tx() argument
1189 container_of(port, struct uart_amba_port, port); in pl011_start_tx()
1195 static void pl011_stop_rx(struct uart_port *port) in pl011_stop_rx() argument
1198 container_of(port, struct uart_amba_port, port); in pl011_stop_rx()
1202 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_stop_rx()
1207 static void pl011_enable_ms(struct uart_port *port) in pl011_enable_ms() argument
1210 container_of(port, struct uart_amba_port, port); in pl011_enable_ms()
1213 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_enable_ms()
1217 __releases(&uap->port.lock) in pl011_rx_chars()
1218 __acquires(&uap->port.lock) in pl011_rx_chars()
1222 spin_unlock(&uap->port.lock); in pl011_rx_chars()
1223 tty_flip_buffer_push(&uap->port.state->port); in pl011_rx_chars()
1230 dev_dbg(uap->port.dev, "could not trigger RX DMA job " in pl011_rx_chars()
1233 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_rx_chars()
1247 spin_lock(&uap->port.lock); in pl011_rx_chars()
1258 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_tx_char()
1261 writew(c, uap->port.membase + UART01x_DR); in pl011_tx_char()
1262 uap->port.icount.tx++; in pl011_tx_char()
1269 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_tx_chars()
1294 readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)) in pl011_tx_chars()
1297 if (uap->port.x_char) { in pl011_tx_chars()
1298 if (!pl011_tx_char(uap, uap->port.x_char)) in pl011_tx_chars()
1300 uap->port.x_char = 0; in pl011_tx_chars()
1303 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { in pl011_tx_chars()
1304 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1319 uart_write_wakeup(&uap->port); in pl011_tx_chars()
1322 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1327 schedule_delayed_work(&uap->tx_softirq_work, uap->port.timeout); in pl011_tx_chars()
1337 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_modem_status()
1346 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); in pl011_modem_status()
1349 uap->port.icount.dsr++; in pl011_modem_status()
1352 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); in pl011_modem_status()
1354 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pl011_modem_status()
1363 spin_lock_irq(&uap->port.lock); in pl011_tx_softirq()
1365 spin_unlock_irq(&uap->port.lock); in pl011_tx_softirq()
1387 spin_lock_irqsave(&uap->port.lock, flags); in pl011_int()
1388 status = readw(uap->port.membase + UART011_MIS); in pl011_int()
1393 writew(0x00, uap->port.membase + UART011_ICR); in pl011_int()
1400 dummy_read = readw(uap->port.membase + UART011_ICR); in pl011_int()
1401 dummy_read = readw(uap->port.membase + UART011_ICR); in pl011_int()
1406 uap->port.membase + UART011_ICR); in pl011_int()
1425 status = readw(uap->port.membase + UART011_MIS); in pl011_int()
1430 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_int()
1435 static unsigned int pl011_tx_empty(struct uart_port *port) in pl011_tx_empty() argument
1438 container_of(port, struct uart_amba_port, port); in pl011_tx_empty()
1439 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl011_tx_empty()
1443 static unsigned int pl011_get_mctrl(struct uart_port *port) in pl011_get_mctrl() argument
1446 container_of(port, struct uart_amba_port, port); in pl011_get_mctrl()
1448 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl011_get_mctrl()
1462 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) in pl011_set_mctrl() argument
1465 container_of(port, struct uart_amba_port, port); in pl011_set_mctrl()
1468 cr = readw(uap->port.membase + UART011_CR); in pl011_set_mctrl()
1488 writew(cr, uap->port.membase + UART011_CR); in pl011_set_mctrl()
1491 static void pl011_break_ctl(struct uart_port *port, int break_state) in pl011_break_ctl() argument
1494 container_of(port, struct uart_amba_port, port); in pl011_break_ctl()
1498 spin_lock_irqsave(&uap->port.lock, flags); in pl011_break_ctl()
1499 lcr_h = readw(uap->port.membase + uap->lcrh_tx); in pl011_break_ctl()
1504 writew(lcr_h, uap->port.membase + uap->lcrh_tx); in pl011_break_ctl()
1505 spin_unlock_irqrestore(&uap->port.lock, flags); in pl011_break_ctl()
1510 static void pl011_quiesce_irqs(struct uart_port *port) in pl011_quiesce_irqs() argument
1513 container_of(port, struct uart_amba_port, port); in pl011_quiesce_irqs()
1514 unsigned char __iomem *regs = uap->port.membase; in pl011_quiesce_irqs()
1533 static int pl011_get_poll_char(struct uart_port *port) in pl011_get_poll_char() argument
1536 container_of(port, struct uart_amba_port, port); in pl011_get_poll_char()
1543 pl011_quiesce_irqs(port); in pl011_get_poll_char()
1545 status = readw(uap->port.membase + UART01x_FR); in pl011_get_poll_char()
1549 return readw(uap->port.membase + UART01x_DR); in pl011_get_poll_char()
1552 static void pl011_put_poll_char(struct uart_port *port, in pl011_put_poll_char() argument
1556 container_of(port, struct uart_amba_port, port); in pl011_put_poll_char()
1558 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_put_poll_char()
1561 writew(ch, uap->port.membase + UART01x_DR); in pl011_put_poll_char()
1566 static int pl011_hwinit(struct uart_port *port) in pl011_hwinit() argument
1569 container_of(port, struct uart_amba_port, port); in pl011_hwinit()
1573 pinctrl_pm_select_default_state(port->dev); in pl011_hwinit()
1582 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_hwinit()
1586 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); in pl011_hwinit()
1592 uap->im = readw(uap->port.membase + UART011_IMSC); in pl011_hwinit()
1593 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); in pl011_hwinit()
1595 if (dev_get_platdata(uap->port.dev)) { in pl011_hwinit()
1598 plat = dev_get_platdata(uap->port.dev); in pl011_hwinit()
1607 writew(lcr_h, uap->port.membase + uap->lcrh_rx); in pl011_write_lcr_h()
1615 writew(0xff, uap->port.membase + UART011_MIS); in pl011_write_lcr_h()
1616 writew(lcr_h, uap->port.membase + uap->lcrh_tx); in pl011_write_lcr_h()
1620 static int pl011_startup(struct uart_port *port) in pl011_startup() argument
1623 container_of(port, struct uart_amba_port, port); in pl011_startup()
1627 retval = pl011_hwinit(port); in pl011_startup()
1631 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_startup()
1636 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); in pl011_startup()
1640 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); in pl011_startup()
1645 spin_lock_irq(&uap->port.lock); in pl011_startup()
1650 writew(cr, uap->port.membase + UART011_CR); in pl011_startup()
1652 spin_unlock_irq(&uap->port.lock); in pl011_startup()
1657 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1667 spin_lock_irq(&uap->port.lock); in pl011_startup()
1670 uap->port.membase + UART011_ICR); in pl011_startup()
1674 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_startup()
1675 spin_unlock_irq(&uap->port.lock); in pl011_startup()
1689 val = readw(uap->port.membase + lcrh); in pl011_shutdown_channel()
1691 writew(val, uap->port.membase + lcrh); in pl011_shutdown_channel()
1694 static void pl011_shutdown(struct uart_port *port) in pl011_shutdown() argument
1697 container_of(port, struct uart_amba_port, port); in pl011_shutdown()
1705 spin_lock_irq(&uap->port.lock); in pl011_shutdown()
1707 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_shutdown()
1708 writew(0xffff, uap->port.membase + UART011_ICR); in pl011_shutdown()
1709 spin_unlock_irq(&uap->port.lock); in pl011_shutdown()
1716 free_irq(uap->port.irq, uap); in pl011_shutdown()
1725 spin_lock_irq(&uap->port.lock); in pl011_shutdown()
1726 cr = readw(uap->port.membase + UART011_CR); in pl011_shutdown()
1730 writew(cr, uap->port.membase + UART011_CR); in pl011_shutdown()
1731 spin_unlock_irq(&uap->port.lock); in pl011_shutdown()
1745 pinctrl_pm_select_sleep_state(port->dev); in pl011_shutdown()
1747 if (dev_get_platdata(uap->port.dev)) { in pl011_shutdown()
1750 plat = dev_get_platdata(uap->port.dev); in pl011_shutdown()
1755 if (uap->port.ops->flush_buffer) in pl011_shutdown()
1756 uap->port.ops->flush_buffer(port); in pl011_shutdown()
1760 pl011_set_termios(struct uart_port *port, struct ktermios *termios, in pl011_set_termios() argument
1764 container_of(port, struct uart_amba_port, port); in pl011_set_termios()
1777 baud = uart_get_baud_rate(port, termios, old, 0, in pl011_set_termios()
1778 port->uartclk / clkdiv); in pl011_set_termios()
1787 if (baud > port->uartclk/16) in pl011_set_termios()
1788 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); in pl011_set_termios()
1790 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); in pl011_set_termios()
1816 spin_lock_irqsave(&port->lock, flags); in pl011_set_termios()
1821 uart_update_timeout(port, termios->c_cflag, baud); in pl011_set_termios()
1823 port->read_status_mask = UART011_DR_OE | 255; in pl011_set_termios()
1825 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_set_termios()
1827 port->read_status_mask |= UART011_DR_BE; in pl011_set_termios()
1832 port->ignore_status_mask = 0; in pl011_set_termios()
1834 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_set_termios()
1836 port->ignore_status_mask |= UART011_DR_BE; in pl011_set_termios()
1842 port->ignore_status_mask |= UART011_DR_OE; in pl011_set_termios()
1849 port->ignore_status_mask |= UART_DUMMY_DR_RX; in pl011_set_termios()
1851 if (UART_ENABLE_MS(port, termios->c_cflag)) in pl011_set_termios()
1852 pl011_enable_ms(port); in pl011_set_termios()
1855 old_cr = readw(port->membase + UART011_CR); in pl011_set_termios()
1856 writew(0, port->membase + UART011_CR); in pl011_set_termios()
1870 if (baud > port->uartclk / 16) in pl011_set_termios()
1889 writew(quot & 0x3f, port->membase + UART011_FBRD); in pl011_set_termios()
1890 writew(quot >> 6, port->membase + UART011_IBRD); in pl011_set_termios()
1899 writew(old_cr, port->membase + UART011_CR); in pl011_set_termios()
1901 spin_unlock_irqrestore(&port->lock, flags); in pl011_set_termios()
1904 static const char *pl011_type(struct uart_port *port) in pl011_type() argument
1907 container_of(port, struct uart_amba_port, port); in pl011_type()
1908 return uap->port.type == PORT_AMBA ? uap->type : NULL; in pl011_type()
1914 static void pl011_release_port(struct uart_port *port) in pl011_release_port() argument
1916 release_mem_region(port->mapbase, SZ_4K); in pl011_release_port()
1922 static int pl011_request_port(struct uart_port *port) in pl011_request_port() argument
1924 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") in pl011_request_port()
1931 static void pl011_config_port(struct uart_port *port, int flags) in pl011_config_port() argument
1934 port->type = PORT_AMBA; in pl011_config_port()
1935 pl011_request_port(port); in pl011_config_port()
1942 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) in pl011_verify_port() argument
1983 static void pl011_console_putchar(struct uart_port *port, int ch) in pl011_console_putchar() argument
1986 container_of(port, struct uart_amba_port, port); in pl011_console_putchar()
1988 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_console_putchar()
1990 writew(ch, uap->port.membase + UART01x_DR); in pl011_console_putchar()
2004 if (uap->port.sysrq) in pl011_console_write()
2007 locked = spin_trylock(&uap->port.lock); in pl011_console_write()
2009 spin_lock(&uap->port.lock); in pl011_console_write()
2014 old_cr = readw(uap->port.membase + UART011_CR); in pl011_console_write()
2017 writew(new_cr, uap->port.membase + UART011_CR); in pl011_console_write()
2019 uart_console_write(&uap->port, s, count, pl011_console_putchar); in pl011_console_write()
2026 status = readw(uap->port.membase + UART01x_FR); in pl011_console_write()
2028 writew(old_cr, uap->port.membase + UART011_CR); in pl011_console_write()
2031 spin_unlock(&uap->port.lock); in pl011_console_write()
2041 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { in pl011_console_get_options()
2044 lcr_h = readw(uap->port.membase + uap->lcrh_tx); in pl011_console_get_options()
2059 ibrd = readw(uap->port.membase + UART011_IBRD); in pl011_console_get_options()
2060 fbrd = readw(uap->port.membase + UART011_FBRD); in pl011_console_get_options()
2062 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); in pl011_console_get_options()
2065 if (readw(uap->port.membase + UART011_CR) in pl011_console_get_options()
2093 pinctrl_pm_select_default_state(uap->port.dev); in pl011_console_setup()
2099 if (dev_get_platdata(uap->port.dev)) { in pl011_console_setup()
2102 plat = dev_get_platdata(uap->port.dev); in pl011_console_setup()
2107 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_console_setup()
2114 return uart_set_options(&uap->port, co, baud, parity, bits, flow); in pl011_console_setup()
2130 static void pl011_putc(struct uart_port *port, int c) in pl011_putc() argument
2132 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2134 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2135 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2143 uart_console_write(&dev->port, s, n, pl011_putc); in pl011_early_write()
2149 if (!device->port.membase) in pl011_early_console_setup()
2239 uap->port.dev = &dev->dev; in pl011_probe()
2240 uap->port.mapbase = dev->res.start; in pl011_probe()
2241 uap->port.membase = base; in pl011_probe()
2242 uap->port.iotype = UPIO_MEM; in pl011_probe()
2243 uap->port.irq = dev->irq[0]; in pl011_probe()
2244 uap->port.fifosize = uap->fifosize; in pl011_probe()
2245 uap->port.ops = &amba_pl011_pops; in pl011_probe()
2246 uap->port.flags = UPF_BOOT_AUTOCONF; in pl011_probe()
2247 uap->port.line = i; in pl011_probe()
2251 writew(0, uap->port.membase + UART011_IMSC); in pl011_probe()
2252 writew(0xffff, uap->port.membase + UART011_ICR); in pl011_probe()
2269 ret = uart_add_one_port(&amba_reg, &uap->port); in pl011_probe()
2284 uart_remove_one_port(&amba_reg, &uap->port); in pl011_remove()
2306 return uart_suspend_port(&amba_reg, &uap->port); in pl011_suspend()
2316 return uart_resume_port(&amba_reg, &uap->port); in pl011_resume()