Lines Matching refs:membase
186 status = readw(uap->port.membase + UART01x_FR); in pl011_fifo_to_tty()
191 ch = readw(uap->port.membase + UART01x_DR) | in pl011_fifo_to_tty()
428 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_callback()
542 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_refill()
578 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_irq()
580 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
590 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
604 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_stop()
630 writew(uap->im, uap->port.membase + in pl011_dma_tx_start()
637 uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
648 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
650 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { in pl011_dma_tx_start()
659 writew(uap->port.x_char, uap->port.membase + UART01x_DR); in pl011_dma_tx_start()
665 writew(dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
693 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_flush_buffer()
733 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_trigger_dma()
737 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_trigger_dma()
796 uap->port.membase + UART011_ICR); in pl011_dma_rx_chars()
844 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_irq()
864 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_irq()
912 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_callback()
925 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_stop()
969 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_poll()
1031 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_startup()
1040 uap->port.membase + ST_UART011_DMAWM); in pl011_dma_startup()
1065 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_dma_shutdown()
1070 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_shutdown()
1171 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_stop_tx()
1181 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_start_tx_pio()
1202 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_stop_rx()
1213 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_enable_ms()
1233 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_rx_chars()
1258 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_tx_char()
1261 writew(c, uap->port.membase + UART01x_DR); in pl011_tx_char()
1294 readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)) in pl011_tx_chars()
1337 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_modem_status()
1388 status = readw(uap->port.membase + UART011_MIS); in pl011_int()
1393 writew(0x00, uap->port.membase + UART011_ICR); in pl011_int()
1400 dummy_read = readw(uap->port.membase + UART011_ICR); in pl011_int()
1401 dummy_read = readw(uap->port.membase + UART011_ICR); in pl011_int()
1406 uap->port.membase + UART011_ICR); in pl011_int()
1425 status = readw(uap->port.membase + UART011_MIS); in pl011_int()
1439 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl011_tx_empty()
1448 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl011_get_mctrl()
1468 cr = readw(uap->port.membase + UART011_CR); in pl011_set_mctrl()
1488 writew(cr, uap->port.membase + UART011_CR); in pl011_set_mctrl()
1499 lcr_h = readw(uap->port.membase + uap->lcrh_tx); in pl011_break_ctl()
1504 writew(lcr_h, uap->port.membase + uap->lcrh_tx); in pl011_break_ctl()
1514 unsigned char __iomem *regs = uap->port.membase; in pl011_quiesce_irqs()
1545 status = readw(uap->port.membase + UART01x_FR); in pl011_get_poll_char()
1549 return readw(uap->port.membase + UART01x_DR); in pl011_get_poll_char()
1558 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_put_poll_char()
1561 writew(ch, uap->port.membase + UART01x_DR); in pl011_put_poll_char()
1586 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); in pl011_hwinit()
1592 uap->im = readw(uap->port.membase + UART011_IMSC); in pl011_hwinit()
1593 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); in pl011_hwinit()
1607 writew(lcr_h, uap->port.membase + uap->lcrh_rx); in pl011_write_lcr_h()
1615 writew(0xff, uap->port.membase + UART011_MIS); in pl011_write_lcr_h()
1616 writew(lcr_h, uap->port.membase + uap->lcrh_tx); in pl011_write_lcr_h()
1631 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_startup()
1640 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); in pl011_startup()
1650 writew(cr, uap->port.membase + UART011_CR); in pl011_startup()
1657 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1670 uap->port.membase + UART011_ICR); in pl011_startup()
1674 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_startup()
1689 val = readw(uap->port.membase + lcrh); in pl011_shutdown_channel()
1691 writew(val, uap->port.membase + lcrh); in pl011_shutdown_channel()
1707 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_shutdown()
1708 writew(0xffff, uap->port.membase + UART011_ICR); in pl011_shutdown()
1726 cr = readw(uap->port.membase + UART011_CR); in pl011_shutdown()
1730 writew(cr, uap->port.membase + UART011_CR); in pl011_shutdown()
1855 old_cr = readw(port->membase + UART011_CR); in pl011_set_termios()
1856 writew(0, port->membase + UART011_CR); in pl011_set_termios()
1889 writew(quot & 0x3f, port->membase + UART011_FBRD); in pl011_set_termios()
1890 writew(quot >> 6, port->membase + UART011_IBRD); in pl011_set_termios()
1899 writew(old_cr, port->membase + UART011_CR); in pl011_set_termios()
1988 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_console_putchar()
1990 writew(ch, uap->port.membase + UART01x_DR); in pl011_console_putchar()
2014 old_cr = readw(uap->port.membase + UART011_CR); in pl011_console_write()
2017 writew(new_cr, uap->port.membase + UART011_CR); in pl011_console_write()
2026 status = readw(uap->port.membase + UART01x_FR); in pl011_console_write()
2028 writew(old_cr, uap->port.membase + UART011_CR); in pl011_console_write()
2041 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { in pl011_console_get_options()
2044 lcr_h = readw(uap->port.membase + uap->lcrh_tx); in pl011_console_get_options()
2059 ibrd = readw(uap->port.membase + UART011_IBRD); in pl011_console_get_options()
2060 fbrd = readw(uap->port.membase + UART011_FBRD); in pl011_console_get_options()
2065 if (readw(uap->port.membase + UART011_CR) in pl011_console_get_options()
2132 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2134 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2135 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2149 if (!device->port.membase) in pl011_early_console_setup()
2241 uap->port.membase = base; in pl011_probe()
2251 writew(0, uap->port.membase + UART011_IMSC); in pl011_probe()
2252 writew(0xffff, uap->port.membase + UART011_ICR); in pl011_probe()