153 	unsigned int		dmacr;		/* dma control reg */  member
419 	u16 dmacr;  in pl011_dma_tx_callback()  local
426 	dmacr = uap->dmacr;  in pl011_dma_tx_callback()
427 	uap->dmacr = dmacr & ~UART011_TXDMAE;  in pl011_dma_tx_callback()
428 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_callback()
439 	if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||  in pl011_dma_tx_callback()
541 	uap->dmacr |= UART011_TXDMAE;  in pl011_dma_tx_refill()
542 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_refill()
577 		uap->dmacr |= UART011_TXDMAE;  in pl011_dma_tx_irq()
578 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_irq()
603 		uap->dmacr &= ~UART011_TXDMAE;  in pl011_dma_tx_stop()
604 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_stop()
618 	u16 dmacr;  in pl011_dma_tx_start()  local
634 		} else if (!(uap->dmacr & UART011_TXDMAE)) {  in pl011_dma_tx_start()
635 			uap->dmacr |= UART011_TXDMAE;  in pl011_dma_tx_start()
636 			writew(uap->dmacr,  in pl011_dma_tx_start()
646 	dmacr = uap->dmacr;  in pl011_dma_tx_start()
647 	uap->dmacr &= ~UART011_TXDMAE;  in pl011_dma_tx_start()
648 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_start()
664 	uap->dmacr = dmacr;  in pl011_dma_tx_start()
665 	writew(dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_tx_start()
692 		uap->dmacr &= ~UART011_TXDMAE;  in pl011_dma_flush_buffer()
693 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_flush_buffer()
732 	uap->dmacr |= UART011_RXDMAE;  in pl011_dma_rx_trigger_dma()
733 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_trigger_dma()
843 	uap->dmacr &= ~UART011_RXDMAE;  in pl011_dma_rx_irq()
844 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_irq()
924 	uap->dmacr &= ~UART011_RXDMAE;  in pl011_dma_rx_stop()
925 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_rx_stop()
1030 	uap->dmacr |= UART011_DMAONERR;  in pl011_dma_startup()
1031 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_startup()
1069 	uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);  in pl011_dma_shutdown()
1070 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);  in pl011_dma_shutdown()