69 	struct uart_port	port;  member
76 static void pl010_stop_tx(struct uart_port *port)  in pl010_stop_tx()  argument
79 		container_of(port, struct uart_amba_port, port);  in pl010_stop_tx()
82 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_tx()
84 	writel(cr, uap->port.membase + UART010_CR);  in pl010_stop_tx()
87 static void pl010_start_tx(struct uart_port *port)  in pl010_start_tx()  argument
90 		container_of(port, struct uart_amba_port, port);  in pl010_start_tx()
93 	cr = readb(uap->port.membase + UART010_CR);  in pl010_start_tx()
95 	writel(cr, uap->port.membase + UART010_CR);  in pl010_start_tx()
98 static void pl010_stop_rx(struct uart_port *port)  in pl010_stop_rx()  argument
101 		container_of(port, struct uart_amba_port, port);  in pl010_stop_rx()
104 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_rx()
106 	writel(cr, uap->port.membase + UART010_CR);  in pl010_stop_rx()
109 static void pl010_disable_ms(struct uart_port *port)  in pl010_disable_ms()  argument
111 	struct uart_amba_port *uap = (struct uart_amba_port *)port;  in pl010_disable_ms()
114 	cr = readb(uap->port.membase + UART010_CR);  in pl010_disable_ms()
116 	writel(cr, uap->port.membase + UART010_CR);  in pl010_disable_ms()
119 static void pl010_enable_ms(struct uart_port *port)  in pl010_enable_ms()  argument
122 		container_of(port, struct uart_amba_port, port);  in pl010_enable_ms()
125 	cr = readb(uap->port.membase + UART010_CR);  in pl010_enable_ms()
127 	writel(cr, uap->port.membase + UART010_CR);  in pl010_enable_ms()
134 	status = readb(uap->port.membase + UART01x_FR);  in pl010_rx_chars()
136 		ch = readb(uap->port.membase + UART01x_DR);  in pl010_rx_chars()
139 		uap->port.icount.rx++;  in pl010_rx_chars()
145 		rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;  in pl010_rx_chars()
147 			writel(0, uap->port.membase + UART01x_ECR);  in pl010_rx_chars()
151 				uap->port.icount.brk++;  in pl010_rx_chars()
152 				if (uart_handle_break(&uap->port))  in pl010_rx_chars()
155 				uap->port.icount.parity++;  in pl010_rx_chars()
157 				uap->port.icount.frame++;  in pl010_rx_chars()
159 				uap->port.icount.overrun++;  in pl010_rx_chars()
161 			rsr &= uap->port.read_status_mask;  in pl010_rx_chars()
171 		if (uart_handle_sysrq_char(&uap->port, ch))  in pl010_rx_chars()
174 		uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);  in pl010_rx_chars()
177 		status = readb(uap->port.membase + UART01x_FR);  in pl010_rx_chars()
179 	spin_unlock(&uap->port.lock);  in pl010_rx_chars()
180 	tty_flip_buffer_push(&uap->port.state->port);  in pl010_rx_chars()
181 	spin_lock(&uap->port.lock);  in pl010_rx_chars()
186 	struct circ_buf *xmit = &uap->port.state->xmit;  in pl010_tx_chars()
189 	if (uap->port.x_char) {  in pl010_tx_chars()
190 		writel(uap->port.x_char, uap->port.membase + UART01x_DR);  in pl010_tx_chars()
191 		uap->port.icount.tx++;  in pl010_tx_chars()
192 		uap->port.x_char = 0;  in pl010_tx_chars()
195 	if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {  in pl010_tx_chars()
196 		pl010_stop_tx(&uap->port);  in pl010_tx_chars()
200 	count = uap->port.fifosize >> 1;  in pl010_tx_chars()
202 		writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);  in pl010_tx_chars()
204 		uap->port.icount.tx++;  in pl010_tx_chars()
210 		uart_write_wakeup(&uap->port);  in pl010_tx_chars()
213 		pl010_stop_tx(&uap->port);  in pl010_tx_chars()
220 	writel(0, uap->port.membase + UART010_ICR);  in pl010_modem_status()
222 	status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_modem_status()
231 		uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);  in pl010_modem_status()
234 		uap->port.icount.dsr++;  in pl010_modem_status()
237 		uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);  in pl010_modem_status()
239 	wake_up_interruptible(&uap->port.state->port.delta_msr_wait);  in pl010_modem_status()
248 	spin_lock(&uap->port.lock);  in pl010_int()
250 	status = readb(uap->port.membase + UART010_IIR);  in pl010_int()
263 			status = readb(uap->port.membase + UART010_IIR);  in pl010_int()
269 	spin_unlock(&uap->port.lock);  in pl010_int()
274 static unsigned int pl010_tx_empty(struct uart_port *port)  in pl010_tx_empty()  argument
277 		container_of(port, struct uart_amba_port, port);  in pl010_tx_empty()
278 	unsigned int status = readb(uap->port.membase + UART01x_FR);  in pl010_tx_empty()
282 static unsigned int pl010_get_mctrl(struct uart_port *port)  in pl010_get_mctrl()  argument
285 		container_of(port, struct uart_amba_port, port);  in pl010_get_mctrl()
289 	status = readb(uap->port.membase + UART01x_FR);  in pl010_get_mctrl()
300 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)  in pl010_set_mctrl()  argument
303 		container_of(port, struct uart_amba_port, port);  in pl010_set_mctrl()
306 		uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);  in pl010_set_mctrl()
309 static void pl010_break_ctl(struct uart_port *port, int break_state)  in pl010_break_ctl()  argument
312 		container_of(port, struct uart_amba_port, port);  in pl010_break_ctl()
316 	spin_lock_irqsave(&uap->port.lock, flags);  in pl010_break_ctl()
317 	lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_break_ctl()
322 	writel(lcr_h, uap->port.membase + UART010_LCRH);  in pl010_break_ctl()
323 	spin_unlock_irqrestore(&uap->port.lock, flags);  in pl010_break_ctl()
326 static int pl010_startup(struct uart_port *port)  in pl010_startup()  argument
329 		container_of(port, struct uart_amba_port, port);  in pl010_startup()
339 	uap->port.uartclk = clk_get_rate(uap->clk);  in pl010_startup()
344 	retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);  in pl010_startup()
351 	uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_startup()
357 	       uap->port.membase + UART010_CR);  in pl010_startup()
367 static void pl010_shutdown(struct uart_port *port)  in pl010_shutdown()  argument
370 		container_of(port, struct uart_amba_port, port);  in pl010_shutdown()
375 	free_irq(uap->port.irq, uap);  in pl010_shutdown()
380 	writel(0, uap->port.membase + UART010_CR);  in pl010_shutdown()
383 	writel(readb(uap->port.membase + UART010_LCRH) &  in pl010_shutdown()
385 	       uap->port.membase + UART010_LCRH);  in pl010_shutdown()
394 pl010_set_termios(struct uart_port *port, struct ktermios *termios,  in pl010_set_termios()  argument
398 		container_of(port, struct uart_amba_port, port);  in pl010_set_termios()
406 	baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);   in pl010_set_termios()
407 	quot = uart_get_divisor(port, baud);  in pl010_set_termios()
430 	if (uap->port.fifosize > 1)  in pl010_set_termios()
433 	spin_lock_irqsave(&uap->port.lock, flags);  in pl010_set_termios()
438 	uart_update_timeout(port, termios->c_cflag, baud);  in pl010_set_termios()
440 	uap->port.read_status_mask = UART01x_RSR_OE;  in pl010_set_termios()
442 		uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;  in pl010_set_termios()
444 		uap->port.read_status_mask |= UART01x_RSR_BE;  in pl010_set_termios()
449 	uap->port.ignore_status_mask = 0;  in pl010_set_termios()
451 		uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;  in pl010_set_termios()
453 		uap->port.ignore_status_mask |= UART01x_RSR_BE;  in pl010_set_termios()
459 			uap->port.ignore_status_mask |= UART01x_RSR_OE;  in pl010_set_termios()
466 		uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;  in pl010_set_termios()
469 	old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;  in pl010_set_termios()
471 	if (UART_ENABLE_MS(port, termios->c_cflag))  in pl010_set_termios()
474 	writel(0, uap->port.membase + UART010_CR);  in pl010_set_termios()
478 	writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);  in pl010_set_termios()
479 	writel(quot & 0xff, uap->port.membase + UART010_LCRL);  in pl010_set_termios()
486 	writel(lcr_h, uap->port.membase + UART010_LCRH);  in pl010_set_termios()
487 	writel(old_cr, uap->port.membase + UART010_CR);  in pl010_set_termios()
489 	spin_unlock_irqrestore(&uap->port.lock, flags);  in pl010_set_termios()
492 static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios)  in pl010_set_ldisc()  argument
495 		port->flags |= UPF_HARDPPS_CD;  in pl010_set_ldisc()
496 		spin_lock_irq(&port->lock);  in pl010_set_ldisc()
497 		pl010_enable_ms(port);  in pl010_set_ldisc()
498 		spin_unlock_irq(&port->lock);  in pl010_set_ldisc()
500 		port->flags &= ~UPF_HARDPPS_CD;  in pl010_set_ldisc()
501 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {  in pl010_set_ldisc()
502 			spin_lock_irq(&port->lock);  in pl010_set_ldisc()
503 			pl010_disable_ms(port);  in pl010_set_ldisc()
504 			spin_unlock_irq(&port->lock);  in pl010_set_ldisc()
509 static const char *pl010_type(struct uart_port *port)  in pl010_type()  argument
511 	return port->type == PORT_AMBA ? "AMBA" : NULL;  in pl010_type()
517 static void pl010_release_port(struct uart_port *port)  in pl010_release_port()  argument
519 	release_mem_region(port->mapbase, UART_PORT_SIZE);  in pl010_release_port()
525 static int pl010_request_port(struct uart_port *port)  in pl010_request_port()  argument
527 	return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")  in pl010_request_port()
534 static void pl010_config_port(struct uart_port *port, int flags)  in pl010_config_port()  argument
537 		port->type = PORT_AMBA;  in pl010_config_port()
538 		pl010_request_port(port);  in pl010_config_port()
545 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)  in pl010_verify_port()  argument
581 static void pl010_console_putchar(struct uart_port *port, int ch)  in pl010_console_putchar()  argument
584 		container_of(port, struct uart_amba_port, port);  in pl010_console_putchar()
588 		status = readb(uap->port.membase + UART01x_FR);  in pl010_console_putchar()
591 	writel(ch, uap->port.membase + UART01x_DR);  in pl010_console_putchar()
605 	old_cr = readb(uap->port.membase + UART010_CR);  in pl010_console_write()
606 	writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);  in pl010_console_write()
608 	uart_console_write(&uap->port, s, count, pl010_console_putchar);  in pl010_console_write()
615 		status = readb(uap->port.membase + UART01x_FR);  in pl010_console_write()
618 	writel(old_cr, uap->port.membase + UART010_CR);  in pl010_console_write()
627 	if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {  in pl010_console_get_options()
629 		lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_console_get_options()
644 		quot = readb(uap->port.membase + UART010_LCRL) |  in pl010_console_get_options()
645 		       readb(uap->port.membase + UART010_LCRM) << 8;  in pl010_console_get_options()
646 		*baud = uap->port.uartclk / (16 * (quot + 1));  in pl010_console_get_options()
674 	uap->port.uartclk = clk_get_rate(uap->clk);  in pl010_console_setup()
681 	return uart_set_options(&uap->port, co, baud, parity, bits, flow);  in pl010_console_setup()
737 	uap->port.dev = &dev->dev;  in pl010_probe()
738 	uap->port.mapbase = dev->res.start;  in pl010_probe()
739 	uap->port.membase = base;  in pl010_probe()
740 	uap->port.iotype = UPIO_MEM;  in pl010_probe()
741 	uap->port.irq = dev->irq[0];  in pl010_probe()
742 	uap->port.fifosize = 16;  in pl010_probe()
743 	uap->port.ops = &amba_pl010_pops;  in pl010_probe()
744 	uap->port.flags = UPF_BOOT_AUTOCONF;  in pl010_probe()
745 	uap->port.line = i;  in pl010_probe()
752 	ret = uart_add_one_port(&amba_reg, &uap->port);  in pl010_probe()
764 	uart_remove_one_port(&amba_reg, &uap->port);  in pl010_remove()
779 		uart_suspend_port(&amba_reg, &uap->port);  in pl010_suspend()
789 		uart_resume_port(&amba_reg, &uap->port);  in pl010_resume()