294 	u8 efr;  in mxser_enable_must_enchance_mode()  local
299 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_enchance_mode()
300 	efr |= MOXA_MUST_EFR_EFRB_ENABLE;  in mxser_enable_must_enchance_mode()
302 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_enchance_mode()
310 	u8 efr;  in mxser_disable_must_enchance_mode()  local
315 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_enchance_mode()
316 	efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;  in mxser_disable_must_enchance_mode()
318 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_enchance_mode()
326 	u8 efr;  in mxser_set_must_xon1_value()  local
331 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_xon1_value()
332 	efr &= ~MOXA_MUST_EFR_BANK_MASK;  in mxser_set_must_xon1_value()
333 	efr |= MOXA_MUST_EFR_BANK0;  in mxser_set_must_xon1_value()
335 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_xon1_value()
343 	u8 efr;  in mxser_set_must_xoff1_value()  local
348 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_xoff1_value()
349 	efr &= ~MOXA_MUST_EFR_BANK_MASK;  in mxser_set_must_xoff1_value()
350 	efr |= MOXA_MUST_EFR_BANK0;  in mxser_set_must_xoff1_value()
352 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_xoff1_value()
360 	u8 efr;  in mxser_set_must_fifo_value()  local
365 	efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_fifo_value()
366 	efr &= ~MOXA_MUST_EFR_BANK_MASK;  in mxser_set_must_fifo_value()
367 	efr |= MOXA_MUST_EFR_BANK1;  in mxser_set_must_fifo_value()
369 	outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_fifo_value()
379 	u8 efr;  in mxser_set_must_enum_value()  local
384 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_enum_value()
385 	efr &= ~MOXA_MUST_EFR_BANK_MASK;  in mxser_set_must_enum_value()
386 	efr |= MOXA_MUST_EFR_BANK2;  in mxser_set_must_enum_value()
388 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_set_must_enum_value()
397 	u8 efr;  in mxser_get_must_hardware_id()  local
402 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_get_must_hardware_id()
403 	efr &= ~MOXA_MUST_EFR_BANK_MASK;  in mxser_get_must_hardware_id()
404 	efr |= MOXA_MUST_EFR_BANK2;  in mxser_get_must_hardware_id()
406 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_get_must_hardware_id()
415 	u8 efr;  in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()  local
420 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
421 	efr &= ~MOXA_MUST_EFR_SF_MASK;  in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
423 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL()
430 	u8 efr;  in mxser_enable_must_tx_software_flow_control()  local
435 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_tx_software_flow_control()
436 	efr &= ~MOXA_MUST_EFR_SF_TX_MASK;  in mxser_enable_must_tx_software_flow_control()
437 	efr |= MOXA_MUST_EFR_SF_TX1;  in mxser_enable_must_tx_software_flow_control()
439 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_tx_software_flow_control()
446 	u8 efr;  in mxser_disable_must_tx_software_flow_control()  local
451 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_tx_software_flow_control()
452 	efr &= ~MOXA_MUST_EFR_SF_TX_MASK;  in mxser_disable_must_tx_software_flow_control()
454 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_tx_software_flow_control()
461 	u8 efr;  in mxser_enable_must_rx_software_flow_control()  local
466 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_rx_software_flow_control()
467 	efr &= ~MOXA_MUST_EFR_SF_RX_MASK;  in mxser_enable_must_rx_software_flow_control()
468 	efr |= MOXA_MUST_EFR_SF_RX1;  in mxser_enable_must_rx_software_flow_control()
470 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_enable_must_rx_software_flow_control()
477 	u8 efr;  in mxser_disable_must_rx_software_flow_control()  local
482 	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_rx_software_flow_control()
483 	efr &= ~MOXA_MUST_EFR_SF_RX_MASK;  in mxser_disable_must_rx_software_flow_control()
485 	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);  in mxser_disable_must_rx_software_flow_control()