Lines Matching refs:spi
168 static inline void mcspi_write_cs_reg(const struct spi_device *spi, in mcspi_write_cs_reg() argument
171 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg()
176 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) in mcspi_read_cs_reg() argument
178 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg()
183 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) in mcspi_cached_chconf0() argument
185 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_cached_chconf0()
190 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) in mcspi_write_chconf0() argument
192 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_chconf0()
195 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); in mcspi_write_chconf0()
196 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); in mcspi_write_chconf0()
209 static void omap2_mcspi_set_dma_req(const struct spi_device *spi, in omap2_mcspi_set_dma_req() argument
214 l = mcspi_cached_chconf0(spi); in omap2_mcspi_set_dma_req()
226 mcspi_write_chconf0(spi, l); in omap2_mcspi_set_dma_req()
229 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) in omap2_mcspi_set_enable() argument
231 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_enable()
240 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_set_enable()
242 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); in omap2_mcspi_set_enable()
245 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) in omap2_mcspi_force_cs() argument
249 l = mcspi_cached_chconf0(spi); in omap2_mcspi_force_cs()
255 mcspi_write_chconf0(spi, l); in omap2_mcspi_force_cs()
276 static void omap2_mcspi_set_fifo(const struct spi_device *spi, in omap2_mcspi_set_fifo() argument
279 struct spi_master *master = spi->master; in omap2_mcspi_set_fifo()
280 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_fifo()
288 chconf = mcspi_cached_chconf0(spi); in omap2_mcspi_set_fifo()
318 mcspi_write_chconf0(spi, chconf); in omap2_mcspi_set_fifo()
331 mcspi_write_chconf0(spi, chconf); in omap2_mcspi_set_fifo()
368 struct spi_device *spi = data; in omap2_mcspi_rx_callback() local
369 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_rx_callback()
370 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_rx_callback()
373 omap2_mcspi_set_dma_req(spi, 1, 0); in omap2_mcspi_rx_callback()
380 struct spi_device *spi = data; in omap2_mcspi_tx_callback() local
381 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_tx_callback()
382 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_tx_callback()
385 omap2_mcspi_set_dma_req(spi, 0, 0); in omap2_mcspi_tx_callback()
390 static void omap2_mcspi_tx_dma(struct spi_device *spi, in omap2_mcspi_tx_dma() argument
398 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_tx_dma()
399 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_tx_dma()
416 tx->callback_param = spi; in omap2_mcspi_tx_dma()
423 omap2_mcspi_set_dma_req(spi, 0, 1); in omap2_mcspi_tx_dma()
428 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, in omap2_mcspi_rx_dma() argument
438 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_rx_dma()
439 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_rx_dma()
440 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_rx_dma()
448 l = mcspi_cached_chconf0(spi); in omap2_mcspi_rx_dma()
475 tx->callback_param = spi; in omap2_mcspi_rx_dma()
483 omap2_mcspi_set_dma_req(spi, 1, 1); in omap2_mcspi_rx_dma()
492 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_rx_dma()
499 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) in omap2_mcspi_rx_dma()
503 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); in omap2_mcspi_rx_dma()
512 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); in omap2_mcspi_rx_dma()
514 omap2_mcspi_set_enable(spi, 1); in omap2_mcspi_rx_dma()
518 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) in omap2_mcspi_rx_dma()
522 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); in omap2_mcspi_rx_dma()
530 dev_err(&spi->dev, "DMA RX last word empty\n"); in omap2_mcspi_rx_dma()
533 omap2_mcspi_set_enable(spi, 1); in omap2_mcspi_rx_dma()
538 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) in omap2_mcspi_txrx_dma() argument
541 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_dma()
555 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_txrx_dma()
556 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_txrx_dma()
557 l = mcspi_cached_chconf0(spi); in omap2_mcspi_txrx_dma()
593 omap2_mcspi_tx_dma(spi, xfer, cfg); in omap2_mcspi_txrx_dma()
596 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); in omap2_mcspi_txrx_dma()
608 dev_err(&spi->dev, "EOW timed out\n"); in omap2_mcspi_txrx_dma()
621 dev_err(&spi->dev, "TXFFE timed out\n"); in omap2_mcspi_txrx_dma()
626 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_dma()
631 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_dma()
638 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) in omap2_mcspi_txrx_pio() argument
641 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_pio()
650 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_txrx_pio()
655 l = mcspi_cached_chconf0(spi); in omap2_mcspi_txrx_pio()
678 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
681 dev_vdbg(&spi->dev, "write-%d %02x\n", in omap2_mcspi_txrx_pio()
688 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
694 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
696 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
700 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
706 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
710 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
725 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
728 dev_vdbg(&spi->dev, "write-%d %04x\n", in omap2_mcspi_txrx_pio()
735 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
741 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
743 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
747 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
753 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
757 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
772 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
775 dev_vdbg(&spi->dev, "write-%d %08x\n", in omap2_mcspi_txrx_pio()
782 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
788 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
790 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
794 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
800 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
804 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
814 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
817 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_pio()
823 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_txrx_pio()
826 omap2_mcspi_set_enable(spi, 1); in omap2_mcspi_txrx_pio()
842 static int omap2_mcspi_setup_transfer(struct spi_device *spi, in omap2_mcspi_setup_transfer() argument
845 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup_transfer()
849 u8 word_len = spi->bits_per_word; in omap2_mcspi_setup_transfer()
850 u32 speed_hz = spi->max_speed_hz; in omap2_mcspi_setup_transfer()
852 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_setup_transfer()
876 l = mcspi_cached_chconf0(spi); in omap2_mcspi_setup_transfer()
896 if (!(spi->mode & SPI_CS_HIGH)) in omap2_mcspi_setup_transfer()
911 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_setup_transfer()
915 if (spi->mode & SPI_CPOL) in omap2_mcspi_setup_transfer()
919 if (spi->mode & SPI_CPHA) in omap2_mcspi_setup_transfer()
924 mcspi_write_chconf0(spi, l); in omap2_mcspi_setup_transfer()
926 cs->mode = spi->mode; in omap2_mcspi_setup_transfer()
928 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", in omap2_mcspi_setup_transfer()
930 (spi->mode & SPI_CPHA) ? "trailing" : "leading", in omap2_mcspi_setup_transfer()
931 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); in omap2_mcspi_setup_transfer()
940 static int omap2_mcspi_request_dma(struct spi_device *spi) in omap2_mcspi_request_dma() argument
942 struct spi_master *master = spi->master; in omap2_mcspi_request_dma()
949 mcspi_dma = mcspi->dma_channels + spi->chip_select; in omap2_mcspi_request_dma()
980 dev_warn(&spi->dev, "not using DMA for McSPI\n"); in omap2_mcspi_request_dma()
984 static int omap2_mcspi_setup(struct spi_device *spi) in omap2_mcspi_setup() argument
987 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_setup()
990 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup()
992 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_setup()
998 cs->base = mcspi->base + spi->chip_select * 0x14; in omap2_mcspi_setup()
999 cs->phys = mcspi->phys + spi->chip_select * 0x14; in omap2_mcspi_setup()
1003 spi->controller_state = cs; in omap2_mcspi_setup()
1009 ret = omap2_mcspi_request_dma(spi); in omap2_mcspi_setup()
1018 ret = omap2_mcspi_setup_transfer(spi, NULL); in omap2_mcspi_setup()
1025 static void omap2_mcspi_cleanup(struct spi_device *spi) in omap2_mcspi_cleanup() argument
1031 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_cleanup()
1033 if (spi->controller_state) { in omap2_mcspi_cleanup()
1035 cs = spi->controller_state; in omap2_mcspi_cleanup()
1041 if (spi->chip_select < spi->master->num_chipselect) { in omap2_mcspi_cleanup()
1042 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_cleanup()
1065 struct spi_device *spi; in omap2_mcspi_work() local
1076 spi = m->spi; in omap2_mcspi_work()
1077 master = spi->master; in omap2_mcspi_work()
1078 mcspi_dma = mcspi->dma_channels + spi->chip_select; in omap2_mcspi_work()
1079 cs = spi->controller_state; in omap2_mcspi_work()
1080 cd = spi->controller_data; in omap2_mcspi_work()
1089 if (spi->mode != cs->mode) in omap2_mcspi_work()
1092 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_work()
1099 (t->speed_hz != spi->max_speed_hz) || in omap2_mcspi_work()
1100 (t->bits_per_word != spi->bits_per_word)) { in omap2_mcspi_work()
1102 status = omap2_mcspi_setup_transfer(spi, t); in omap2_mcspi_work()
1105 if (t->speed_hz == spi->max_speed_hz && in omap2_mcspi_work()
1106 t->bits_per_word == spi->bits_per_word) in omap2_mcspi_work()
1114 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); in omap2_mcspi_work()
1119 omap2_mcspi_force_cs(spi, 1); in omap2_mcspi_work()
1123 chconf = mcspi_cached_chconf0(spi); in omap2_mcspi_work()
1138 mcspi_write_chconf0(spi, chconf); in omap2_mcspi_work()
1145 omap2_mcspi_set_fifo(spi, t, 1); in omap2_mcspi_work()
1147 omap2_mcspi_set_enable(spi, 1); in omap2_mcspi_work()
1156 count = omap2_mcspi_txrx_dma(spi, t); in omap2_mcspi_work()
1158 count = omap2_mcspi_txrx_pio(spi, t); in omap2_mcspi_work()
1172 omap2_mcspi_force_cs(spi, 0); in omap2_mcspi_work()
1176 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_work()
1179 omap2_mcspi_set_fifo(spi, t, 0); in omap2_mcspi_work()
1184 status = omap2_mcspi_setup_transfer(spi, NULL); in omap2_mcspi_work()
1188 omap2_mcspi_force_cs(spi, 0); in omap2_mcspi_work()
1195 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); in omap2_mcspi_work()
1198 omap2_mcspi_set_enable(spi, 0); in omap2_mcspi_work()
1201 omap2_mcspi_set_fifo(spi, t, 0); in omap2_mcspi_work()
1209 struct spi_device *spi; in omap2_mcspi_transfer_one_message() local
1215 spi = m->spi; in omap2_mcspi_transfer_one_message()
1217 mcspi_dma = mcspi->dma_channels + spi->chip_select; in omap2_mcspi_transfer_one_message()