46 static int mid_spi_dma_init(struct dw_spi *dws)  in mid_spi_dma_init()  argument
49 	struct dw_dma_slave *tx = dws->dma_tx;  in mid_spi_dma_init()
50 	struct dw_dma_slave *rx = dws->dma_rx;  in mid_spi_dma_init()
66 	dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);  in mid_spi_dma_init()
67 	if (!dws->rxchan)  in mid_spi_dma_init()
69 	dws->master->dma_rx = dws->rxchan;  in mid_spi_dma_init()
73 	dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);  in mid_spi_dma_init()
74 	if (!dws->txchan)  in mid_spi_dma_init()
76 	dws->master->dma_tx = dws->txchan;  in mid_spi_dma_init()
78 	dws->dma_inited = 1;  in mid_spi_dma_init()
82 	dma_release_channel(dws->rxchan);  in mid_spi_dma_init()
87 static void mid_spi_dma_exit(struct dw_spi *dws)  in mid_spi_dma_exit()  argument
89 	if (!dws->dma_inited)  in mid_spi_dma_exit()
92 	dmaengine_terminate_all(dws->txchan);  in mid_spi_dma_exit()
93 	dma_release_channel(dws->txchan);  in mid_spi_dma_exit()
95 	dmaengine_terminate_all(dws->rxchan);  in mid_spi_dma_exit()
96 	dma_release_channel(dws->rxchan);  in mid_spi_dma_exit()
99 static irqreturn_t dma_transfer(struct dw_spi *dws)  in dma_transfer()  argument
101 	u16 irq_status = dw_readl(dws, DW_SPI_ISR);  in dma_transfer()
106 	dw_readl(dws, DW_SPI_ICR);  in dma_transfer()
107 	spi_reset_chip(dws);  in dma_transfer()
109 	dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);  in dma_transfer()
110 	dws->master->cur_msg->status = -EIO;  in dma_transfer()
111 	spi_finalize_current_transfer(dws->master);  in dma_transfer()
118 	struct dw_spi *dws = spi_master_get_devdata(master);  in mid_spi_can_dma()  local
120 	if (!dws->dma_inited)  in mid_spi_can_dma()
123 	return xfer->len > dws->fifo_len;  in mid_spi_can_dma()
141 	struct dw_spi *dws = arg;  in dw_spi_dma_tx_done()  local
143 	clear_bit(TX_BUSY, &dws->dma_chan_busy);  in dw_spi_dma_tx_done()
144 	if (test_bit(RX_BUSY, &dws->dma_chan_busy))  in dw_spi_dma_tx_done()
146 	spi_finalize_current_transfer(dws->master);  in dw_spi_dma_tx_done()
149 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,  in dw_spi_dma_prepare_tx()  argument
159 	txconf.dst_addr = dws->dma_addr;  in dw_spi_dma_prepare_tx()
162 	txconf.dst_addr_width = convert_dma_width(dws->dma_width);  in dw_spi_dma_prepare_tx()
165 	dmaengine_slave_config(dws->txchan, &txconf);  in dw_spi_dma_prepare_tx()
167 	txdesc = dmaengine_prep_slave_sg(dws->txchan,  in dw_spi_dma_prepare_tx()
176 	txdesc->callback_param = dws;  in dw_spi_dma_prepare_tx()
187 	struct dw_spi *dws = arg;  in dw_spi_dma_rx_done()  local
189 	clear_bit(RX_BUSY, &dws->dma_chan_busy);  in dw_spi_dma_rx_done()
190 	if (test_bit(TX_BUSY, &dws->dma_chan_busy))  in dw_spi_dma_rx_done()
192 	spi_finalize_current_transfer(dws->master);  in dw_spi_dma_rx_done()
195 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,  in dw_spi_dma_prepare_rx()  argument
205 	rxconf.src_addr = dws->dma_addr;  in dw_spi_dma_prepare_rx()
208 	rxconf.src_addr_width = convert_dma_width(dws->dma_width);  in dw_spi_dma_prepare_rx()
211 	dmaengine_slave_config(dws->rxchan, &rxconf);  in dw_spi_dma_prepare_rx()
213 	rxdesc = dmaengine_prep_slave_sg(dws->rxchan,  in dw_spi_dma_prepare_rx()
222 	rxdesc->callback_param = dws;  in dw_spi_dma_prepare_rx()
227 static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)  in mid_spi_dma_setup()  argument
231 	dw_writel(dws, DW_SPI_DMARDLR, 0xf);  in mid_spi_dma_setup()
232 	dw_writel(dws, DW_SPI_DMATDLR, 0x10);  in mid_spi_dma_setup()
238 	dw_writel(dws, DW_SPI_DMACR, dma_ctrl);  in mid_spi_dma_setup()
241 	spi_umask_intr(dws, SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI);  in mid_spi_dma_setup()
243 	dws->transfer_handler = dma_transfer;  in mid_spi_dma_setup()
248 static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)  in mid_spi_dma_transfer()  argument
253 	txdesc = dw_spi_dma_prepare_tx(dws, xfer);  in mid_spi_dma_transfer()
256 	rxdesc = dw_spi_dma_prepare_rx(dws, xfer);  in mid_spi_dma_transfer()
260 		set_bit(RX_BUSY, &dws->dma_chan_busy);  in mid_spi_dma_transfer()
262 		dma_async_issue_pending(dws->rxchan);  in mid_spi_dma_transfer()
266 		set_bit(TX_BUSY, &dws->dma_chan_busy);  in mid_spi_dma_transfer()
268 		dma_async_issue_pending(dws->txchan);  in mid_spi_dma_transfer()
274 static void mid_spi_dma_stop(struct dw_spi *dws)  in mid_spi_dma_stop()  argument
276 	if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {  in mid_spi_dma_stop()
277 		dmaengine_terminate_all(dws->txchan);  in mid_spi_dma_stop()
278 		clear_bit(TX_BUSY, &dws->dma_chan_busy);  in mid_spi_dma_stop()
280 	if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {  in mid_spi_dma_stop()
281 		dmaengine_terminate_all(dws->rxchan);  in mid_spi_dma_stop()
282 		clear_bit(RX_BUSY, &dws->dma_chan_busy);  in mid_spi_dma_stop()
307 int dw_spi_mid_init(struct dw_spi *dws)  in dw_spi_mid_init()  argument
317 	clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));  in dw_spi_mid_init()
320 	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);  in dw_spi_mid_init()
325 	dws->dma_tx = &mid_dma_tx;  in dw_spi_mid_init()
326 	dws->dma_rx = &mid_dma_rx;  in dw_spi_mid_init()
327 	dws->dma_ops = &mid_dma_ops;  in dw_spi_mid_init()