Lines Matching refs:ctl
128 bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE); in bfin_spi_enable()
133 bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE); in bfin_spi_disable()
214 bfin_write(&drv_data->regs->ctl, chip->ctl_reg); in bfin_spi_restore_state()
495 u16 cr = bfin_read(&drv_data->regs->ctl); in bfin_spi_dma_irq_handler()
498 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */ in bfin_spi_dma_irq_handler()
499 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */ in bfin_spi_dma_irq_handler()
653 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE); in bfin_spi_pump_transfers()
655 bfin_write(&drv_data->regs->ctl, cr); in bfin_spi_pump_transfers()
720 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX); in bfin_spi_pump_transfers()
775 bfin_write(&drv_data->regs->ctl, cr); in bfin_spi_pump_transfers()
789 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD); in bfin_spi_pump_transfers()
1343 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); in bfin_spi_probe()
1416 drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl); in bfin_spi_suspend()
1422 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); in bfin_spi_suspend()
1433 bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg); in bfin_spi_resume()