45 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)  in ath79_spi_rr()  argument
47 	return ioread32(sp->base + reg);  in ath79_spi_rr()
50 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)  in ath79_spi_wr()  argument
52 	iowrite32(val, sp->base + reg);  in ath79_spi_wr()
60 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)  in ath79_spi_delay()  argument
62 	if (nsecs > sp->rrw_delay)  in ath79_spi_delay()
63 		ndelay(nsecs - sp->rrw_delay);  in ath79_spi_delay()
68 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);  in ath79_spi_chipselect()  local
74 			sp->ioc_base |= AR71XX_SPI_IOC_CLK;  in ath79_spi_chipselect()
76 			sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;  in ath79_spi_chipselect()
78 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);  in ath79_spi_chipselect()
88 			sp->ioc_base |= AR71XX_SPI_IOC_CS0;  in ath79_spi_chipselect()
90 			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;  in ath79_spi_chipselect()
92 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);  in ath79_spi_chipselect()
97 static void ath79_spi_enable(struct ath79_spi *sp)  in ath79_spi_enable()  argument
100 	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);  in ath79_spi_enable()
103 	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);  in ath79_spi_enable()
104 	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);  in ath79_spi_enable()
107 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);  in ath79_spi_enable()
110 static void ath79_spi_disable(struct ath79_spi *sp)  in ath79_spi_disable()  argument
113 	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);  in ath79_spi_disable()
115 	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);  in ath79_spi_disable()
178 	struct ath79_spi *sp = ath79_spidev_to_sp(spi);  in ath79_spi_txrx_mode0()  local
179 	u32 ioc = sp->ioc_base;  in ath79_spi_txrx_mode0()
191 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);  in ath79_spi_txrx_mode0()
192 		ath79_spi_delay(sp, nsecs);  in ath79_spi_txrx_mode0()
193 		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);  in ath79_spi_txrx_mode0()
194 		ath79_spi_delay(sp, nsecs);  in ath79_spi_txrx_mode0()
196 			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);  in ath79_spi_txrx_mode0()
201 	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);  in ath79_spi_txrx_mode0()
207 	struct ath79_spi *sp;  in ath79_spi_probe()  local
213 	master = spi_alloc_master(&pdev->dev, sizeof(*sp));  in ath79_spi_probe()
219 	sp = spi_master_get_devdata(master);  in ath79_spi_probe()
220 	platform_set_drvdata(pdev, sp);  in ath79_spi_probe()
232 	sp->bitbang.master = master;  in ath79_spi_probe()
233 	sp->bitbang.chipselect = ath79_spi_chipselect;  in ath79_spi_probe()
234 	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;  in ath79_spi_probe()
235 	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;  in ath79_spi_probe()
236 	sp->bitbang.flags = SPI_CS_HIGH;  in ath79_spi_probe()
244 	sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));  in ath79_spi_probe()
245 	if (!sp->base) {  in ath79_spi_probe()
250 	sp->clk = devm_clk_get(&pdev->dev, "ahb");  in ath79_spi_probe()
251 	if (IS_ERR(sp->clk)) {  in ath79_spi_probe()
252 		ret = PTR_ERR(sp->clk);  in ath79_spi_probe()
256 	ret = clk_enable(sp->clk);  in ath79_spi_probe()
260 	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);  in ath79_spi_probe()
266 	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;  in ath79_spi_probe()
268 		sp->rrw_delay);  in ath79_spi_probe()
270 	ath79_spi_enable(sp);  in ath79_spi_probe()
271 	ret = spi_bitbang_start(&sp->bitbang);  in ath79_spi_probe()
278 	ath79_spi_disable(sp);  in ath79_spi_probe()
280 	clk_disable(sp->clk);  in ath79_spi_probe()
282 	spi_master_put(sp->bitbang.master);  in ath79_spi_probe()
289 	struct ath79_spi *sp = platform_get_drvdata(pdev);  in ath79_spi_remove()  local
291 	spi_bitbang_stop(&sp->bitbang);  in ath79_spi_remove()
292 	ath79_spi_disable(sp);  in ath79_spi_remove()
293 	clk_disable(sp->clk);  in ath79_spi_remove()
294 	spi_master_put(sp->bitbang.master);  in ath79_spi_remove()