Lines Matching refs:mmio_base
295 void __iomem *mmio_base; /* iomapped PCI memory space */ member
510 writel(hba->req_head, hba->mmio_base + IMR0); in stex_send_cmd()
511 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); in stex_send_cmd()
512 readl(hba->mmio_base + IDBL); /* flush */ in stex_send_cmd()
540 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); in stex_ss_send_cmd()
541 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */ in stex_ss_send_cmd()
542 writel(addr, hba->mmio_base + YH2I_REQ); in stex_ss_send_cmd()
543 readl(hba->mmio_base + YH2I_REQ); /* flush */ in stex_ss_send_cmd()
753 void __iomem *base = hba->mmio_base; in stex_mu_intr()
841 void __iomem *base = hba->mmio_base; in stex_intr()
942 void __iomem *base = hba->mmio_base; in stex_ss_intr()
966 void __iomem *base = hba->mmio_base; in stex_common_handshake()
1050 void __iomem *base = hba->mmio_base; in stex_ss_handshake()
1149 base = hba->mmio_base; in stex_abort()
1235 base = hba->mmio_base; in stex_yos_reset()
1262 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT); in stex_ss_reset()
1263 readl(hba->mmio_base + YH2I_INT); in stex_ss_reset()
1554 hba->mmio_base = pci_ioremap_bar(pdev, 0); in stex_probe()
1555 if ( !hba->mmio_base) { in stex_probe()
1692 iounmap(hba->mmio_base); in stex_probe()
1755 iounmap(hba->mmio_base); in stex_hba_free()