Lines Matching refs:uint32_t

263 	uint32_t mbox_cmd;
265 	uint32_t pid;
272         uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
289 	uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
295 	int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
296 			  struct ddb_entry *ddb_entry, uint32_t state);
310 	uint32_t default_time2wait;	  /* Default Min time between
366 			uint32_t data_size;
370 			uint32_t status;
371 			uint32_t pid;
372 			uint32_t data_size;
380 	uint32_t flash_conf_off;
381 	uint32_t flash_data_off;
383 	uint32_t fdt_wrt_disable;
384 	uint32_t fdt_erase_cmd;
385 	uint32_t fdt_block_size;
386 	uint32_t fdt_unprotect_sec_cmd;
387 	uint32_t fdt_protect_sec_cmd;
389 	uint32_t flt_region_flt;
390 	uint32_t flt_region_fdt;
391 	uint32_t flt_region_boot;
392 	uint32_t flt_region_bootload;
393 	uint32_t flt_region_fw;
395 	uint32_t flt_iscsi_param;
396 	uint32_t flt_region_chap;
397 	uint32_t flt_chap_size;
398 	uint32_t flt_region_ddb;
399 	uint32_t flt_ddb_size;
403 	uint32_t int_vec_bit;
404 	uint32_t tgt_status_reg;
405 	uint32_t tgt_mask_reg;
406 	uint32_t pci_int_reg;
435 	void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
444 	uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
445 	void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
446 	int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
447 	int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
451 	void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
456 	uint32_t size;
457 	uint32_t size_cmask_02;
458 	uint32_t size_cmask_04;
459 	uint32_t size_cmask_08;
460 	uint32_t size_cmask_10;
461 	uint32_t size_cmask_FF;
462 	uint32_t version;
474 	uint32_t ipv6_options;
475 	uint32_t ipv6_addl_options;
503 	uint32_t ipv6_nd_reach_time;
504 	uint32_t ipv6_nd_rexmit_timer;
505 	uint32_t ipv6_nd_stale_timeout;
507 	uint32_t ipv6_gw_advrt_mtu;
607 	uint32_t tot_ddbs;
631 	uint32_t eeprom_cmd_data;
641 	uint32_t bytes_xfered;
642 	uint32_t spurious_int_count;
643 	uint32_t aborted_io_count;
644 	uint32_t io_timeout_count;
645 	uint32_t mailbox_timeout_count;
646 	uint32_t seconds_since_last_intr;
647 	uint32_t seconds_since_last_heartbeat;
648 	uint32_t mac_index;
652 	uint32_t firmware_version[2];
653 	uint32_t patch_number;
654 	uint32_t build_number;
655 	uint32_t board_id;
669 	uint32_t firmware_state;
670 	uint32_t addl_fw_state;
678 	uint32_t timer_active;
682 	uint32_t retry_reset_ha_cnt;
683 	uint32_t isp_reset_timer;	/* reset test timer */
684 	uint32_t nic_reset_timer;	/* simulated nic reset test timer */
727 	volatile uint32_t mbox_status[MBOX_REG_COUNT];
745 	uint32_t crb_win;
746 	uint32_t curr_window;
747 	uint32_t ddr_mn_window;
759 	uint32_t fw_heartbeat_counter;
766 	uint32_t nx_dev_init_timeout;
767 	uint32_t nx_reset_timeout;
769 	uint32_t fw_dump_size;
770 	uint32_t fw_dump_capture_mask;
772 	uint32_t fw_dump_tmplt_size;
773 	uint32_t fw_dump_skip_size;
784 	uint32_t fw_uptime_secs;  /* seconds elapsed since fw bootup */
785 	uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */
788 	uint32_t flash_state;
821 	uint32_t mrb_index;
823 	uint32_t *reg_tbl;
828 	uint32_t pf_bit;
844 	uint32_t req_len;
847 	uint32_t resp_len;
1061 				      const uint32_t crb_reg)  in qla4_8xxx_rd_direct()
1067 				       const uint32_t crb_reg,  in qla4_8xxx_wr_direct()
1068 				       const uint32_t value)  in qla4_8xxx_wr_direct()