16 uint32_t qla4_83xx_rd_reg(struct scsi_qla_host *ha, ulong addr)  in qla4_83xx_rd_reg()
21 void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val)  in qla4_83xx_wr_reg()
26 static int qla4_83xx_set_win_base(struct scsi_qla_host *ha, uint32_t addr)  in qla4_83xx_set_win_base()
28 	uint32_t val;  in qla4_83xx_set_win_base()
42 int qla4_83xx_rd_reg_indirect(struct scsi_qla_host *ha, uint32_t addr,  in qla4_83xx_rd_reg_indirect()
43 			      uint32_t *data)  in qla4_83xx_rd_reg_indirect()
58 int qla4_83xx_wr_reg_indirect(struct scsi_qla_host *ha, uint32_t addr,  in qla4_83xx_wr_reg_indirect()
59 			      uint32_t data)  in qla4_83xx_wr_reg_indirect()
78 	uint32_t lock_status = 0;  in qla4_83xx_flash_lock()
108 int qla4_83xx_flash_read_u32(struct scsi_qla_host *ha, uint32_t flash_addr,  in qla4_83xx_flash_read_u32()
112 	uint32_t u32_word;  in qla4_83xx_flash_read_u32()
113 	uint32_t addr = flash_addr;  in qla4_83xx_flash_read_u32()
159 				      uint32_t flash_addr, uint8_t *p_data,  in qla4_83xx_lockless_flash_read_u32()
162 	uint32_t i;  in qla4_83xx_lockless_flash_read_u32()
163 	uint32_t u32_word;  in qla4_83xx_lockless_flash_read_u32()
164 	uint32_t flash_offset;  in qla4_83xx_lockless_flash_read_u32()
165 	uint32_t addr = flash_addr;  in qla4_83xx_lockless_flash_read_u32()
186 	if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >  in qla4_83xx_lockless_flash_read_u32()
258 	uint32_t lock = 0, lockid;  in qla4_83xx_lock_recovery()
310 	uint32_t status = 0;  in qla4_83xx_drv_lock()
312 	uint32_t first_owner = 0;  in qla4_83xx_drv_lock()
313 	uint32_t tmo_owner = 0;  in qla4_83xx_drv_lock()
314 	uint32_t lock_id;  in qla4_83xx_drv_lock()
315 	uint32_t func_num;  in qla4_83xx_drv_lock()
316 	uint32_t lock_cnt;  in qla4_83xx_drv_lock()
394 	uint32_t idc_ctrl;  in qla4_83xx_set_idc_dontreset()
405 	uint32_t idc_ctrl;  in qla4_83xx_clear_idc_dontreset()
416 	uint32_t idc_ctrl;  in qla4_83xx_idc_dontreset()
439 	uint32_t drv_active;  in qla4_83xx_can_perform_reset()
440 	uint32_t dev_part, dev_part1, dev_part2;  in qla4_83xx_can_perform_reset()
510 	uint32_t dev_state, drv_state, drv_active;  in qla4_83xx_need_reset_handler()
582 	uint32_t idc_params, ret_val;  in qla4_83xx_get_idc_param()
625 	uint32_t src, count, size;  in qla4_83xx_copy_bootloader()
649 						    size / sizeof(uint32_t));  in qla4_83xx_copy_bootloader()
659 	ret_val = qla4_8xxx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache,  in qla4_83xx_copy_bootloader()
679 	uint32_t val, ret_val = QLA_ERROR;  in qla4_83xx_check_cmd_peg_status()
707 static int qla4_83xx_poll_reg(struct scsi_qla_host *ha, uint32_t addr,  in qla4_83xx_poll_reg()
708 			      int duration, uint32_t test_mask,  in qla4_83xx_poll_reg()
709 			      uint32_t test_result)  in qla4_83xx_poll_reg()
711 	uint32_t value;  in qla4_83xx_poll_reg()
746 	uint32_t sum =  0;  in qla4_83xx_reset_seq_checksum_test()
776 	uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;  in qla4_83xx_read_reset_template()
777 	uint32_t ret_val;  in qla4_83xx_read_reset_template()
791 				    sizeof(uint32_t);  in qla4_83xx_read_reset_template()
810 	tmplt_hdr_size = ha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);  in qla4_83xx_read_reset_template()
821 			      ha->reset_tmplt.hdr->hdr_size) / sizeof(uint32_t);  in qla4_83xx_read_reset_template()
872 					 uint32_t raddr, uint32_t waddr)  in qla4_83xx_read_write_crb_reg()
874 	uint32_t value;  in qla4_83xx_read_write_crb_reg()
891 static void qla4_83xx_rmw_crb_reg(struct scsi_qla_host *ha, uint32_t raddr,  in qla4_83xx_rmw_crb_reg()
892 				  uint32_t waddr,  in qla4_83xx_rmw_crb_reg()
895 	uint32_t value;  in qla4_83xx_rmw_crb_reg()
917 	uint32_t i;  in qla4_83xx_write_list()
925 			udelay((uint32_t)(p_hdr->delay));  in qla4_83xx_write_list()
933 	uint32_t i;  in qla4_83xx_read_write_list()
941 			udelay((uint32_t)(p_hdr->delay));  in qla4_83xx_read_write_list()
951 	uint32_t i;  in qla4_83xx_poll_list()
952 	uint32_t value;  in qla4_83xx_poll_list()
989 	uint32_t i;  in qla4_83xx_poll_write_list()
1020 	uint32_t i;  in qla4_83xx_read_modify_write()
1031 			udelay((uint32_t)(p_hdr->delay));  in qla4_83xx_read_modify_write()
1039 		mdelay((uint32_t)((long)p_hdr->delay));  in qla4_83xx_pause()
1049 	uint32_t i;  in qla4_83xx_poll_read_list()
1050 	uint32_t value;  in qla4_83xx_poll_read_list()
1203 	uint32_t idc_ctrl;  in qla4_83xx_restart()
1270 	uint32_t mb_int, ret;  in qla4_83xx_disable_mbox_intrs()
1296 	uint32_t mb_int;  in qla4_83xx_enable_mbox_intrs()
1314 void qla4_83xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,  in qla4_83xx_queue_mbox_cmd()
1349 	uint32_t dev_state;  in qla4_83xx_isp_reset()
1582 	uint32_t drv_active;  in qla4_83xx_is_detached()