Lines Matching refs:uint32_t
242 uint32_t test_mask;
243 uint32_t test_value;
248 uint32_t test_mask;
249 uint32_t xor_value;
250 uint32_t or_value;
259 uint32_t arg1;
260 uint32_t arg2;
265 uint32_t dr_addr;
266 uint32_t dr_value;
267 uint32_t ar_addr;
268 uint32_t ar_value;
275 uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
289 uint32_t entry_type;
290 uint32_t entry_size;
291 uint32_t entry_capture_size;
303 uint32_t addr;
309 uint32_t data_size;
310 uint32_t op_count;
319 uint32_t value_1;
320 uint32_t value_2;
321 uint32_t value_3;
326 uint32_t tag_reg_addr;
331 uint32_t data_size;
332 uint32_t op_count;
333 uint32_t control_addr;
339 uint32_t read_addr;
350 uint32_t rsvd_0;
351 uint32_t rsvd_1;
352 uint32_t data_size;
353 uint32_t op_count;
354 uint32_t rsvd_2;
355 uint32_t rsvd_3;
356 uint32_t read_addr;
357 uint32_t read_addr_stride;
363 uint32_t rsvd[6];
364 uint32_t read_addr;
365 uint32_t read_data_size;
371 uint32_t desc_card_addr;
374 uint32_t start_dma_cmd;
376 uint32_t read_addr;
377 uint32_t read_data_size;
383 uint32_t rsvd[6];
384 uint32_t read_addr;
385 uint32_t read_data_size;
391 uint32_t select_addr;
392 uint32_t rsvd_0;
393 uint32_t data_size;
394 uint32_t op_count;
395 uint32_t select_value;
396 uint32_t select_value_stride;
397 uint32_t read_addr;
398 uint32_t rsvd_1;
404 uint32_t select_addr;
409 uint32_t data_size;
410 uint32_t op_count;
411 uint32_t rsvd_1;
412 uint32_t rsvd_2;
413 uint32_t read_addr;
424 uint32_t select_addr;
425 uint32_t read_addr;
426 uint32_t select_value;
429 uint32_t poll_wait;
430 uint32_t poll_mask;
431 uint32_t data_size;
432 uint32_t rsvd_1;
437 uint32_t addr_1;
438 uint32_t value;
442 uint32_t poll;
443 uint32_t mask;
444 uint32_t modify_mask;
445 uint32_t data_size;
446 uint32_t rsvd;
453 uint32_t addr_1;
454 uint32_t addr_2;
455 uint32_t value_1;
459 uint32_t poll;
460 uint32_t mask;
461 uint32_t value_2;
462 uint32_t data_size;
468 uint32_t addr_1;
469 uint32_t addr_2;
470 uint32_t value_1;
471 uint32_t value_2;
472 uint32_t poll;
473 uint32_t mask;
474 uint32_t data_size;
475 uint32_t rsvd;
482 uint32_t select_addr_1;
483 uint32_t select_addr_2;
484 uint32_t select_value_1;
485 uint32_t select_value_2;
486 uint32_t op_count;
487 uint32_t select_value_mask;
488 uint32_t read_addr;
497 uint32_t addr_1;
498 uint32_t addr_2;
499 uint32_t value_1;
500 uint32_t value_2;
501 uint32_t poll_wait;
502 uint32_t poll_mask;
503 uint32_t modify_mask;
504 uint32_t data_size;
509 uint32_t request_desc; /* IDC request descriptor */
510 uint32_t info1; /* IDC additional info */
511 uint32_t info2; /* IDC additional info */
512 uint32_t info3; /* IDC additional info */
536 static const uint32_t qla8044_reg_tbl[] = {
569 uint32_t entry_type;
570 uint32_t first_entry_offset;
571 uint32_t size_of_template;
572 uint32_t capture_debug_level;
573 uint32_t num_of_entries;
574 uint32_t version;
575 uint32_t driver_timestamp;
576 uint32_t checksum;
578 uint32_t driver_capture_mask;
579 uint32_t driver_info_word2;
580 uint32_t driver_info_word3;
581 uint32_t driver_info_word4;
583 uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
584 uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
585 uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
590 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */