Lines Matching refs:ha
355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) in qla82xx_pci_set_crbwindow_2M() argument
358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_pci_set_crbwindow_2M()
360 ha->crb_win = CRB_HI(*off); in qla82xx_pci_set_crbwindow_2M()
361 writel(ha->crb_win, in qla82xx_pci_set_crbwindow_2M()
362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla82xx_pci_set_crbwindow_2M()
368 (CRB_WINDOW_2M + ha->nx_pcibase)); in qla82xx_pci_set_crbwindow_2M()
369 if (win_read != ha->crb_win) { in qla82xx_pci_set_crbwindow_2M()
373 __func__, ha->crb_win, win_read, *off); in qla82xx_pci_set_crbwindow_2M()
375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; in qla82xx_pci_set_crbwindow_2M()
379 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) in qla82xx_pci_set_crbwindow() argument
381 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_pci_set_crbwindow()
392 if (ha->curr_window != 0) in qla82xx_pci_set_crbwindow()
401 if (ha->curr_window != 1) in qla82xx_pci_set_crbwindow()
420 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) in qla82xx_pci_get_crb_addr_2M() argument
429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; in qla82xx_pci_get_crb_addr_2M()
442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; in qla82xx_pci_get_crb_addr_2M()
450 static int qla82xx_crb_win_lock(struct qla_hw_data *ha) in qla82xx_crb_win_lock() argument
456 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); in qla82xx_crb_win_lock()
463 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); in qla82xx_crb_win_lock()
468 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) in qla82xx_wr_32() argument
473 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); in qla82xx_wr_32()
478 write_lock_irqsave(&ha->hw_lock, flags); in qla82xx_wr_32()
479 qla82xx_crb_win_lock(ha); in qla82xx_wr_32()
480 qla82xx_pci_set_crbwindow_2M(ha, &off); in qla82xx_wr_32()
486 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); in qla82xx_wr_32()
487 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_wr_32()
493 qla82xx_rd_32(struct qla_hw_data *ha, ulong off) in qla82xx_rd_32() argument
499 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); in qla82xx_rd_32()
504 write_lock_irqsave(&ha->hw_lock, flags); in qla82xx_rd_32()
505 qla82xx_crb_win_lock(ha); in qla82xx_rd_32()
506 qla82xx_pci_set_crbwindow_2M(ha, &off); in qla82xx_rd_32()
511 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); in qla82xx_rd_32()
512 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_rd_32()
518 int qla82xx_idc_lock(struct qla_hw_data *ha) in qla82xx_idc_lock() argument
525 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); in qla82xx_idc_lock()
545 void qla82xx_idc_unlock(struct qla_hw_data *ha) in qla82xx_idc_unlock() argument
547 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); in qla82xx_idc_unlock()
558 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, in qla82xx_pci_mem_bound_check() argument
574 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) in qla82xx_pci_set_window() argument
578 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_pci_set_window()
584 ha->ddr_mn_window = window; in qla82xx_pci_set_window()
585 qla82xx_wr_32(ha, in qla82xx_pci_set_window()
586 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); in qla82xx_pci_set_window()
587 win_read = qla82xx_rd_32(ha, in qla82xx_pci_set_window()
588 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); in qla82xx_pci_set_window()
604 ha->ddr_mn_window = window; in qla82xx_pci_set_window()
605 qla82xx_wr_32(ha, in qla82xx_pci_set_window()
606 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); in qla82xx_pci_set_window()
607 win_read = qla82xx_rd_32(ha, in qla82xx_pci_set_window()
608 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); in qla82xx_pci_set_window()
622 ha->qdr_sn_window = window; in qla82xx_pci_set_window()
623 qla82xx_wr_32(ha, in qla82xx_pci_set_window()
624 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); in qla82xx_pci_set_window()
625 win_read = qla82xx_rd_32(ha, in qla82xx_pci_set_window()
626 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); in qla82xx_pci_set_window()
650 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, in qla82xx_pci_is_same_window() argument
671 if (ha->qdr_sn_window == window) in qla82xx_pci_is_same_window()
677 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, in qla82xx_pci_mem_read_direct() argument
687 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_pci_mem_read_direct()
689 write_lock_irqsave(&ha->hw_lock, flags); in qla82xx_pci_mem_read_direct()
695 start = qla82xx_pci_set_window(ha, off); in qla82xx_pci_mem_read_direct()
697 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla82xx_pci_mem_read_direct()
698 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_pci_mem_read_direct()
706 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_pci_mem_read_direct()
707 mem_base = pci_resource_start(ha->pdev, 0); in qla82xx_pci_mem_read_direct()
722 write_lock_irqsave(&ha->hw_lock, flags); in qla82xx_pci_mem_read_direct()
741 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_pci_mem_read_direct()
749 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, in qla82xx_pci_mem_write_direct() argument
759 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_pci_mem_write_direct()
761 write_lock_irqsave(&ha->hw_lock, flags); in qla82xx_pci_mem_write_direct()
767 start = qla82xx_pci_set_window(ha, off); in qla82xx_pci_mem_write_direct()
769 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla82xx_pci_mem_write_direct()
770 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_pci_mem_write_direct()
778 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_pci_mem_write_direct()
779 mem_base = pci_resource_start(ha->pdev, 0); in qla82xx_pci_mem_write_direct()
793 write_lock_irqsave(&ha->hw_lock, flags); in qla82xx_pci_mem_write_direct()
812 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_pci_mem_write_direct()
847 qla82xx_rom_lock(struct qla_hw_data *ha) in qla82xx_rom_lock() argument
851 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_rom_lock()
855 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); in qla82xx_rom_lock()
859 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); in qla82xx_rom_lock()
862 __func__, ha->portnum, lock_owner); in qla82xx_rom_lock()
867 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum); in qla82xx_rom_lock()
872 qla82xx_rom_unlock(struct qla_hw_data *ha) in qla82xx_rom_unlock() argument
874 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); in qla82xx_rom_unlock()
875 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); in qla82xx_rom_unlock()
879 qla82xx_wait_rom_busy(struct qla_hw_data *ha) in qla82xx_wait_rom_busy() argument
883 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_wait_rom_busy()
886 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); in qla82xx_wait_rom_busy()
900 qla82xx_wait_rom_done(struct qla_hw_data *ha) in qla82xx_wait_rom_done() argument
904 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_wait_rom_done()
907 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); in qla82xx_wait_rom_done()
921 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) in qla82xx_md_rw_32() argument
925 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), in qla82xx_md_rw_32()
929 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla82xx_md_rw_32()
934 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), in qla82xx_md_rw_32()
938 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); in qla82xx_md_rw_32()
944 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) in qla82xx_do_rom_fast_read() argument
947 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); in qla82xx_do_rom_fast_read()
948 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE + in qla82xx_do_rom_fast_read()
955 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) in qla82xx_rom_fast_read() argument
959 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_rom_fast_read()
961 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { in qla82xx_rom_fast_read()
967 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); in qla82xx_rom_fast_read()
973 ret = qla82xx_do_rom_fast_read(ha, addr, valp); in qla82xx_rom_fast_read()
974 qla82xx_rom_unlock(ha); in qla82xx_rom_fast_read()
979 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) in qla82xx_read_status_reg() argument
981 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_read_status_reg()
982 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); in qla82xx_read_status_reg()
983 qla82xx_wait_rom_busy(ha); in qla82xx_read_status_reg()
984 if (qla82xx_wait_rom_done(ha)) { in qla82xx_read_status_reg()
989 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); in qla82xx_read_status_reg()
994 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) in qla82xx_flash_wait_write_finish() argument
1000 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_flash_wait_write_finish()
1002 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla82xx_flash_wait_write_finish()
1004 ret = qla82xx_read_status_reg(ha, &val); in qla82xx_flash_wait_write_finish()
1019 qla82xx_flash_set_write_enable(struct qla_hw_data *ha) in qla82xx_flash_set_write_enable() argument
1022 qla82xx_wait_rom_busy(ha); in qla82xx_flash_set_write_enable()
1023 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla82xx_flash_set_write_enable()
1024 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); in qla82xx_flash_set_write_enable()
1025 qla82xx_wait_rom_busy(ha); in qla82xx_flash_set_write_enable()
1026 if (qla82xx_wait_rom_done(ha)) in qla82xx_flash_set_write_enable()
1028 if (qla82xx_read_status_reg(ha, &val) != 0) in qla82xx_flash_set_write_enable()
1036 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) in qla82xx_write_status_reg() argument
1038 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_write_status_reg()
1039 if (qla82xx_flash_set_write_enable(ha)) in qla82xx_write_status_reg()
1041 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); in qla82xx_write_status_reg()
1042 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); in qla82xx_write_status_reg()
1043 if (qla82xx_wait_rom_done(ha)) { in qla82xx_write_status_reg()
1048 return qla82xx_flash_wait_write_finish(ha); in qla82xx_write_status_reg()
1052 qla82xx_write_disable_flash(struct qla_hw_data *ha) in qla82xx_write_disable_flash() argument
1054 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_write_disable_flash()
1055 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); in qla82xx_write_disable_flash()
1056 if (qla82xx_wait_rom_done(ha)) { in qla82xx_write_disable_flash()
1065 ql82xx_rom_lock_d(struct qla_hw_data *ha) in ql82xx_rom_lock_d() argument
1069 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in ql82xx_rom_lock_d()
1071 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { in ql82xx_rom_lock_d()
1077 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); in ql82xx_rom_lock_d()
1086 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, in qla82xx_write_flash_dword() argument
1090 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_write_flash_dword()
1092 ret = ql82xx_rom_lock_d(ha); in qla82xx_write_flash_dword()
1099 if (qla82xx_flash_set_write_enable(ha)) in qla82xx_write_flash_dword()
1102 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); in qla82xx_write_flash_dword()
1103 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); in qla82xx_write_flash_dword()
1104 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); in qla82xx_write_flash_dword()
1105 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); in qla82xx_write_flash_dword()
1106 qla82xx_wait_rom_busy(ha); in qla82xx_write_flash_dword()
1107 if (qla82xx_wait_rom_done(ha)) { in qla82xx_write_flash_dword()
1114 ret = qla82xx_flash_wait_write_finish(ha); in qla82xx_write_flash_dword()
1117 qla82xx_rom_unlock(ha); in qla82xx_write_flash_dword()
1132 struct qla_hw_data *ha = vha->hw; in qla82xx_pinit_from_rom() local
1140 qla82xx_rom_lock(ha); in qla82xx_pinit_from_rom()
1143 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); in qla82xx_pinit_from_rom()
1144 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); in qla82xx_pinit_from_rom()
1145 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); in qla82xx_pinit_from_rom()
1146 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); in qla82xx_pinit_from_rom()
1147 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); in qla82xx_pinit_from_rom()
1148 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); in qla82xx_pinit_from_rom()
1151 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); in qla82xx_pinit_from_rom()
1153 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); in qla82xx_pinit_from_rom()
1155 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); in qla82xx_pinit_from_rom()
1157 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); in qla82xx_pinit_from_rom()
1159 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); in qla82xx_pinit_from_rom()
1161 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); in qla82xx_pinit_from_rom()
1164 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); in qla82xx_pinit_from_rom()
1165 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); in qla82xx_pinit_from_rom()
1168 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); in qla82xx_pinit_from_rom()
1171 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); in qla82xx_pinit_from_rom()
1172 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); in qla82xx_pinit_from_rom()
1173 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); in qla82xx_pinit_from_rom()
1174 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); in qla82xx_pinit_from_rom()
1175 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); in qla82xx_pinit_from_rom()
1176 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); in qla82xx_pinit_from_rom()
1179 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); in qla82xx_pinit_from_rom()
1180 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); in qla82xx_pinit_from_rom()
1181 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); in qla82xx_pinit_from_rom()
1182 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); in qla82xx_pinit_from_rom()
1183 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); in qla82xx_pinit_from_rom()
1189 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); in qla82xx_pinit_from_rom()
1191 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); in qla82xx_pinit_from_rom()
1192 qla82xx_rom_unlock(ha); in qla82xx_pinit_from_rom()
1199 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || in qla82xx_pinit_from_rom()
1200 qla82xx_rom_fast_read(ha, 4, &n) != 0) { in qla82xx_pinit_from_rom()
1230 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || in qla82xx_pinit_from_rom()
1231 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { in qla82xx_pinit_from_rom()
1281 qla82xx_wr_32(ha, off, buf[i].data); in qla82xx_pinit_from_rom()
1298 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); in qla82xx_pinit_from_rom()
1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); in qla82xx_pinit_from_rom()
1300 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); in qla82xx_pinit_from_rom()
1303 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); in qla82xx_pinit_from_rom()
1304 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); in qla82xx_pinit_from_rom()
1305 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); in qla82xx_pinit_from_rom()
1306 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); in qla82xx_pinit_from_rom()
1307 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); in qla82xx_pinit_from_rom()
1308 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); in qla82xx_pinit_from_rom()
1309 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); in qla82xx_pinit_from_rom()
1310 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); in qla82xx_pinit_from_rom()
1315 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, in qla82xx_pci_mem_write_2M() argument
1330 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) in qla82xx_pci_mem_write_2M()
1331 return qla82xx_pci_mem_write_direct(ha, in qla82xx_pci_mem_write_2M()
1346 if (qla82xx_pci_mem_read_2M(ha, off8 + in qla82xx_pci_mem_write_2M()
1381 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); in qla82xx_pci_mem_write_2M()
1383 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); in qla82xx_pci_mem_write_2M()
1385 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); in qla82xx_pci_mem_write_2M()
1387 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); in qla82xx_pci_mem_write_2M()
1389 qla82xx_wr_32(ha, mem_crb + in qla82xx_pci_mem_write_2M()
1392 qla82xx_wr_32(ha, mem_crb + in qla82xx_pci_mem_write_2M()
1396 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); in qla82xx_pci_mem_write_2M()
1398 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); in qla82xx_pci_mem_write_2M()
1401 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); in qla82xx_pci_mem_write_2M()
1408 dev_err(&ha->pdev->dev, in qla82xx_pci_mem_write_2M()
1419 qla82xx_fw_load_from_flash(struct qla_hw_data *ha) in qla82xx_fw_load_from_flash() argument
1423 long flashaddr = ha->flt_region_bootload << 2; in qla82xx_fw_load_from_flash()
1430 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || in qla82xx_fw_load_from_flash()
1431 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { in qla82xx_fw_load_from_flash()
1435 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); in qla82xx_fw_load_from_flash()
1443 read_lock(&ha->hw_lock); in qla82xx_fw_load_from_flash()
1444 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla82xx_fw_load_from_flash()
1445 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla82xx_fw_load_from_flash()
1446 read_unlock(&ha->hw_lock); in qla82xx_fw_load_from_flash()
1451 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, in qla82xx_pci_mem_read_2M() argument
1467 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) in qla82xx_pci_mem_read_2M()
1468 return qla82xx_pci_mem_read_direct(ha, in qla82xx_pci_mem_read_2M()
1482 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); in qla82xx_pci_mem_read_2M()
1484 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); in qla82xx_pci_mem_read_2M()
1486 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); in qla82xx_pci_mem_read_2M()
1488 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); in qla82xx_pci_mem_read_2M()
1491 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); in qla82xx_pci_mem_read_2M()
1498 dev_err(&ha->pdev->dev, in qla82xx_pci_mem_read_2M()
1506 temp = qla82xx_rd_32(ha, in qla82xx_pci_mem_read_2M()
1563 qla82xx_get_data_desc(struct qla_hw_data *ha, in qla82xx_get_data_desc() argument
1566 const u8 *unirom = ha->hablob->fw->data; in qla82xx_get_data_desc()
1567 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); in qla82xx_get_data_desc()
1582 qla82xx_get_bootld_offset(struct qla_hw_data *ha) in qla82xx_get_bootld_offset() argument
1587 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { in qla82xx_get_bootld_offset()
1588 uri_desc = qla82xx_get_data_desc(ha, in qla82xx_get_bootld_offset()
1594 return (u8 *)&ha->hablob->fw->data[offset]; in qla82xx_get_bootld_offset()
1598 qla82xx_get_fw_size(struct qla_hw_data *ha) in qla82xx_get_fw_size() argument
1602 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { in qla82xx_get_fw_size()
1603 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, in qla82xx_get_fw_size()
1609 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); in qla82xx_get_fw_size()
1613 qla82xx_get_fw_offs(struct qla_hw_data *ha) in qla82xx_get_fw_offs() argument
1618 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { in qla82xx_get_fw_offs()
1619 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, in qla82xx_get_fw_offs()
1625 return (u8 *)&ha->hablob->fw->data[offset]; in qla82xx_get_fw_offs()
1648 qla82xx_iospace_config(struct qla_hw_data *ha) in qla82xx_iospace_config() argument
1652 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { in qla82xx_iospace_config()
1653 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, in qla82xx_iospace_config()
1659 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { in qla82xx_iospace_config()
1660 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, in qla82xx_iospace_config()
1665 len = pci_resource_len(ha->pdev, 0); in qla82xx_iospace_config()
1666 ha->nx_pcibase = in qla82xx_iospace_config()
1667 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); in qla82xx_iospace_config()
1668 if (!ha->nx_pcibase) { in qla82xx_iospace_config()
1669 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, in qla82xx_iospace_config()
1675 if (IS_QLA8044(ha)) { in qla82xx_iospace_config()
1676 ha->iobase = in qla82xx_iospace_config()
1677 (device_reg_t *)((uint8_t *)ha->nx_pcibase); in qla82xx_iospace_config()
1678 } else if (IS_QLA82XX(ha)) { in qla82xx_iospace_config()
1679 ha->iobase = in qla82xx_iospace_config()
1680 (device_reg_t *)((uint8_t *)ha->nx_pcibase + in qla82xx_iospace_config()
1681 0xbc000 + (ha->pdev->devfn << 11)); in qla82xx_iospace_config()
1685 ha->nxdb_wr_ptr = in qla82xx_iospace_config()
1686 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + in qla82xx_iospace_config()
1687 (ha->pdev->devfn << 12)), 4); in qla82xx_iospace_config()
1688 if (!ha->nxdb_wr_ptr) { in qla82xx_iospace_config()
1689 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, in qla82xx_iospace_config()
1697 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + in qla82xx_iospace_config()
1698 (ha->pdev->devfn * 8); in qla82xx_iospace_config()
1700 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? in qla82xx_iospace_config()
1705 ha->max_req_queues = ha->max_rsp_queues = 1; in qla82xx_iospace_config()
1706 ha->msix_count = ha->max_rsp_queues + 1; in qla82xx_iospace_config()
1707 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, in qla82xx_iospace_config()
1710 (void *)ha->nx_pcibase, ha->iobase, in qla82xx_iospace_config()
1711 ha->max_req_queues, ha->msix_count); in qla82xx_iospace_config()
1712 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, in qla82xx_iospace_config()
1715 (void *)ha->nx_pcibase, ha->iobase, in qla82xx_iospace_config()
1716 ha->max_req_queues, ha->msix_count); in qla82xx_iospace_config()
1736 struct qla_hw_data *ha = vha->hw; in qla82xx_pci_config() local
1739 pci_set_master(ha->pdev); in qla82xx_pci_config()
1740 ret = pci_set_mwi(ha->pdev); in qla82xx_pci_config()
1741 ha->chip_revision = ha->pdev->revision; in qla82xx_pci_config()
1744 ha->chip_revision); in qla82xx_pci_config()
1757 struct qla_hw_data *ha = vha->hw; in qla82xx_reset_chip() local
1758 ha->isp_ops->disable_intrs(ha); in qla82xx_reset_chip()
1763 struct qla_hw_data *ha = vha->hw; in qla82xx_config_rings() local
1764 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; in qla82xx_config_rings()
1766 struct req_que *req = ha->req_q_map[0]; in qla82xx_config_rings()
1767 struct rsp_que *rsp = ha->rsp_q_map[0]; in qla82xx_config_rings()
1770 icb = (struct init_cb_81xx *)ha->init_cb; in qla82xx_config_rings()
1786 qla82xx_fw_load_from_blob(struct qla_hw_data *ha) in qla82xx_fw_load_from_blob() argument
1794 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); in qla82xx_fw_load_from_blob()
1799 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) in qla82xx_fw_load_from_blob()
1805 size = (__force u32)qla82xx_get_fw_size(ha) / 8; in qla82xx_fw_load_from_blob()
1806 ptr64 = (u64 *)qla82xx_get_fw_offs(ha); in qla82xx_fw_load_from_blob()
1811 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) in qla82xx_fw_load_from_blob()
1822 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); in qla82xx_fw_load_from_blob()
1824 read_lock(&ha->hw_lock); in qla82xx_fw_load_from_blob()
1825 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla82xx_fw_load_from_blob()
1826 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla82xx_fw_load_from_blob()
1827 read_unlock(&ha->hw_lock); in qla82xx_fw_load_from_blob()
1832 qla82xx_set_product_offset(struct qla_hw_data *ha) in qla82xx_set_product_offset() argument
1835 const uint8_t *unirom = ha->hablob->fw->data; in qla82xx_set_product_offset()
1839 uint8_t chiprev = ha->chip_revision; in qla82xx_set_product_offset()
1862 ha->file_prd_off = offset; in qla82xx_set_product_offset()
1874 struct qla_hw_data *ha = vha->hw; in qla82xx_validate_firmware_blob() local
1875 const struct firmware *fw = ha->hablob->fw; in qla82xx_validate_firmware_blob()
1877 ha->fw_type = fw_type; in qla82xx_validate_firmware_blob()
1880 if (qla82xx_set_product_offset(ha)) in qla82xx_validate_firmware_blob()
1898 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) in qla82xx_check_cmdpeg_state() argument
1902 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_check_cmdpeg_state()
1905 read_lock(&ha->hw_lock); in qla82xx_check_cmdpeg_state()
1906 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); in qla82xx_check_cmdpeg_state()
1907 read_unlock(&ha->hw_lock); in qla82xx_check_cmdpeg_state()
1929 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); in qla82xx_check_cmdpeg_state()
1930 read_lock(&ha->hw_lock); in qla82xx_check_cmdpeg_state()
1931 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); in qla82xx_check_cmdpeg_state()
1932 read_unlock(&ha->hw_lock); in qla82xx_check_cmdpeg_state()
1937 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) in qla82xx_check_rcvpeg_state() argument
1941 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_check_rcvpeg_state()
1944 read_lock(&ha->hw_lock); in qla82xx_check_rcvpeg_state()
1945 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); in qla82xx_check_rcvpeg_state()
1946 read_unlock(&ha->hw_lock); in qla82xx_check_rcvpeg_state()
1967 read_lock(&ha->hw_lock); in qla82xx_check_rcvpeg_state()
1968 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); in qla82xx_check_rcvpeg_state()
1969 read_unlock(&ha->hw_lock); in qla82xx_check_rcvpeg_state()
1987 struct qla_hw_data *ha = vha->hw; in qla82xx_mbx_completion() local
1988 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; in qla82xx_mbx_completion()
1992 ha->flags.mbox_int = 1; in qla82xx_mbx_completion()
1993 ha->mailbox_out[0] = mb0; in qla82xx_mbx_completion()
1995 for (cnt = 1; cnt < ha->mbx_count; cnt++) { in qla82xx_mbx_completion()
1996 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla82xx_mbx_completion()
2000 if (!ha->mcp) in qla82xx_mbx_completion()
2019 struct qla_hw_data *ha; in qla82xx_intr_handler() local
2034 ha = rsp->hw; in qla82xx_intr_handler()
2036 if (!ha->flags.msi_enabled) { in qla82xx_intr_handler()
2037 status = qla82xx_rd_32(ha, ISR_INT_VECTOR); in qla82xx_intr_handler()
2038 if (!(status & ha->nx_legacy_intr.int_vec_bit)) in qla82xx_intr_handler()
2041 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); in qla82xx_intr_handler()
2047 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); in qla82xx_intr_handler()
2050 qla82xx_rd_32(ha, ISR_INT_VECTOR); in qla82xx_intr_handler()
2051 qla82xx_rd_32(ha, ISR_INT_VECTOR); in qla82xx_intr_handler()
2053 reg = &ha->iobase->isp82; in qla82xx_intr_handler()
2055 spin_lock_irqsave(&ha->hardware_lock, flags); in qla82xx_intr_handler()
2056 vha = pci_get_drvdata(ha->pdev); in qla82xx_intr_handler()
2090 qla2x00_handle_mbx_completion(ha, status); in qla82xx_intr_handler()
2091 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla82xx_intr_handler()
2093 if (!ha->flags.msi_enabled) in qla82xx_intr_handler()
2094 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla82xx_intr_handler()
2103 struct qla_hw_data *ha; in qla82xx_msix_default() local
2118 ha = rsp->hw; in qla82xx_msix_default()
2120 reg = &ha->iobase->isp82; in qla82xx_msix_default()
2122 spin_lock_irqsave(&ha->hardware_lock, flags); in qla82xx_msix_default()
2123 vha = pci_get_drvdata(ha->pdev); in qla82xx_msix_default()
2159 qla2x00_handle_mbx_completion(ha, status); in qla82xx_msix_default()
2160 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla82xx_msix_default()
2169 struct qla_hw_data *ha; in qla82xx_msix_rsp_q() local
2182 ha = rsp->hw; in qla82xx_msix_rsp_q()
2183 reg = &ha->iobase->isp82; in qla82xx_msix_rsp_q()
2184 spin_lock_irqsave(&ha->hardware_lock, flags); in qla82xx_msix_rsp_q()
2185 vha = pci_get_drvdata(ha->pdev); in qla82xx_msix_rsp_q()
2192 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla82xx_msix_rsp_q()
2200 struct qla_hw_data *ha; in qla82xx_poll() local
2215 ha = rsp->hw; in qla82xx_poll()
2217 reg = &ha->iobase->isp82; in qla82xx_poll()
2218 spin_lock_irqsave(&ha->hardware_lock, flags); in qla82xx_poll()
2219 vha = pci_get_drvdata(ha->pdev); in qla82xx_poll()
2253 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla82xx_poll()
2257 qla82xx_enable_intrs(struct qla_hw_data *ha) in qla82xx_enable_intrs() argument
2259 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_enable_intrs()
2261 spin_lock_irq(&ha->hardware_lock); in qla82xx_enable_intrs()
2262 if (IS_QLA8044(ha)) in qla82xx_enable_intrs()
2263 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); in qla82xx_enable_intrs()
2265 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla82xx_enable_intrs()
2266 spin_unlock_irq(&ha->hardware_lock); in qla82xx_enable_intrs()
2267 ha->interrupts_on = 1; in qla82xx_enable_intrs()
2271 qla82xx_disable_intrs(struct qla_hw_data *ha) in qla82xx_disable_intrs() argument
2273 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_disable_intrs()
2275 spin_lock_irq(&ha->hardware_lock); in qla82xx_disable_intrs()
2276 if (IS_QLA8044(ha)) in qla82xx_disable_intrs()
2277 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1); in qla82xx_disable_intrs()
2279 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); in qla82xx_disable_intrs()
2280 spin_unlock_irq(&ha->hardware_lock); in qla82xx_disable_intrs()
2281 ha->interrupts_on = 0; in qla82xx_disable_intrs()
2284 void qla82xx_init_flags(struct qla_hw_data *ha) in qla82xx_init_flags() argument
2289 rwlock_init(&ha->hw_lock); in qla82xx_init_flags()
2290 ha->qdr_sn_window = -1; in qla82xx_init_flags()
2291 ha->ddr_mn_window = -1; in qla82xx_init_flags()
2292 ha->curr_window = 255; in qla82xx_init_flags()
2293 ha->portnum = PCI_FUNC(ha->pdev->devfn); in qla82xx_init_flags()
2294 nx_legacy_intr = &legacy_intr[ha->portnum]; in qla82xx_init_flags()
2295 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; in qla82xx_init_flags()
2296 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; in qla82xx_init_flags()
2297 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; in qla82xx_init_flags()
2298 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; in qla82xx_init_flags()
2306 struct qla_hw_data *ha = vha->hw; in qla82xx_set_idc_version() local
2308 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_set_idc_version()
2309 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) { in qla82xx_set_idc_version()
2310 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, in qla82xx_set_idc_version()
2315 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION); in qla82xx_set_idc_version()
2328 struct qla_hw_data *ha = vha->hw; in qla82xx_set_drv_active() local
2330 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_set_drv_active()
2334 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, in qla82xx_set_drv_active()
2336 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_set_drv_active()
2338 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); in qla82xx_set_drv_active()
2339 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); in qla82xx_set_drv_active()
2343 qla82xx_clear_drv_active(struct qla_hw_data *ha) in qla82xx_clear_drv_active() argument
2347 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_clear_drv_active()
2348 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); in qla82xx_clear_drv_active()
2349 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); in qla82xx_clear_drv_active()
2353 qla82xx_need_reset(struct qla_hw_data *ha) in qla82xx_need_reset() argument
2358 if (ha->flags.nic_core_reset_owner) in qla82xx_need_reset()
2361 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_need_reset()
2362 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); in qla82xx_need_reset()
2368 qla82xx_set_rst_ready(struct qla_hw_data *ha) in qla82xx_set_rst_ready() argument
2371 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_set_rst_ready()
2373 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_set_rst_ready()
2377 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); in qla82xx_set_rst_ready()
2378 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_set_rst_ready()
2380 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); in qla82xx_set_rst_ready()
2383 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); in qla82xx_set_rst_ready()
2387 qla82xx_clear_rst_ready(struct qla_hw_data *ha) in qla82xx_clear_rst_ready() argument
2391 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_clear_rst_ready()
2392 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); in qla82xx_clear_rst_ready()
2393 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); in qla82xx_clear_rst_ready()
2397 qla82xx_set_qsnt_ready(struct qla_hw_data *ha) in qla82xx_set_qsnt_ready() argument
2401 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_set_qsnt_ready()
2402 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); in qla82xx_set_qsnt_ready()
2403 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); in qla82xx_set_qsnt_ready()
2409 struct qla_hw_data *ha = vha->hw; in qla82xx_clear_qsnt_ready() local
2412 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_clear_qsnt_ready()
2413 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); in qla82xx_clear_qsnt_ready()
2414 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); in qla82xx_clear_qsnt_ready()
2422 struct qla_hw_data *ha = vha->hw; in qla82xx_load_fw() local
2432 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); in qla82xx_load_fw()
2434 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); in qla82xx_load_fw()
2447 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { in qla82xx_load_fw()
2461 blob = ha->hablob = qla2x00_request_firmware(vha); in qla82xx_load_fw()
2480 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { in qla82xx_load_fw()
2501 struct qla_hw_data *ha = vha->hw; in qla82xx_start_firmware() local
2504 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); in qla82xx_start_firmware()
2509 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); in qla82xx_start_firmware()
2510 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); in qla82xx_start_firmware()
2513 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); in qla82xx_start_firmware()
2514 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); in qla82xx_start_firmware()
2523 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { in qla82xx_start_firmware()
2530 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); in qla82xx_start_firmware()
2531 ha->link_width = (lnk >> 4) & 0x3f; in qla82xx_start_firmware()
2534 return qla82xx_check_rcvpeg_state(ha); in qla82xx_start_firmware()
2543 struct qla_hw_data *ha = vha->hw; in qla82xx_read_flash_data() local
2547 if (qla82xx_rom_fast_read(ha, faddr, &val)) { in qla82xx_read_flash_data()
2559 qla82xx_unprotect_flash(struct qla_hw_data *ha) in qla82xx_unprotect_flash() argument
2563 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_unprotect_flash()
2565 ret = ql82xx_rom_lock_d(ha); in qla82xx_unprotect_flash()
2572 ret = qla82xx_read_status_reg(ha, &val); in qla82xx_unprotect_flash()
2577 ret = qla82xx_write_status_reg(ha, val); in qla82xx_unprotect_flash()
2580 qla82xx_write_status_reg(ha, val); in qla82xx_unprotect_flash()
2583 if (qla82xx_write_disable_flash(ha) != 0) in qla82xx_unprotect_flash()
2588 qla82xx_rom_unlock(ha); in qla82xx_unprotect_flash()
2593 qla82xx_protect_flash(struct qla_hw_data *ha) in qla82xx_protect_flash() argument
2597 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_protect_flash()
2599 ret = ql82xx_rom_lock_d(ha); in qla82xx_protect_flash()
2606 ret = qla82xx_read_status_reg(ha, &val); in qla82xx_protect_flash()
2612 ret = qla82xx_write_status_reg(ha, val); in qla82xx_protect_flash()
2617 if (qla82xx_write_disable_flash(ha) != 0) in qla82xx_protect_flash()
2621 qla82xx_rom_unlock(ha); in qla82xx_protect_flash()
2626 qla82xx_erase_sector(struct qla_hw_data *ha, int addr) in qla82xx_erase_sector() argument
2629 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_erase_sector()
2631 ret = ql82xx_rom_lock_d(ha); in qla82xx_erase_sector()
2638 qla82xx_flash_set_write_enable(ha); in qla82xx_erase_sector()
2639 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); in qla82xx_erase_sector()
2640 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); in qla82xx_erase_sector()
2641 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); in qla82xx_erase_sector()
2643 if (qla82xx_wait_rom_done(ha)) { in qla82xx_erase_sector()
2649 ret = qla82xx_flash_wait_write_finish(ha); in qla82xx_erase_sector()
2651 qla82xx_rom_unlock(ha); in qla82xx_erase_sector()
2678 struct qla_hw_data *ha = vha->hw; in qla82xx_write_flash_data() local
2685 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, in qla82xx_write_flash_data()
2695 rest_addr = ha->fdt_block_size - 1; in qla82xx_write_flash_data()
2698 ret = qla82xx_unprotect_flash(ha); in qla82xx_write_flash_data()
2709 ret = qla82xx_erase_sector(ha, faddr); in qla82xx_write_flash_data()
2724 (ha->flash_data_off | faddr), in qla82xx_write_flash_data()
2730 (ha->flash_data_off | faddr), in qla82xx_write_flash_data()
2735 dma_free_coherent(&ha->pdev->dev, in qla82xx_write_flash_data()
2746 ret = qla82xx_write_flash_dword(ha, faddr, in qla82xx_write_flash_data()
2756 ret = qla82xx_protect_flash(ha); in qla82xx_write_flash_data()
2762 dma_free_coherent(&ha->pdev->dev, in qla82xx_write_flash_data()
2790 struct qla_hw_data *ha = vha->hw; in qla82xx_start_iocbs() local
2791 struct req_que *req = ha->req_q_map[0]; in qla82xx_start_iocbs()
2803 reg = &ha->iobase->isp82; in qla82xx_start_iocbs()
2804 dbval = 0x04 | (ha->portnum << 5); in qla82xx_start_iocbs()
2808 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); in qla82xx_start_iocbs()
2810 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); in qla82xx_start_iocbs()
2812 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_iocbs()
2813 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, in qla82xx_start_iocbs()
2821 qla82xx_rom_lock_recovery(struct qla_hw_data *ha) in qla82xx_rom_lock_recovery() argument
2823 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla82xx_rom_lock_recovery()
2826 if (qla82xx_rom_lock(ha)) { in qla82xx_rom_lock_recovery()
2827 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID); in qla82xx_rom_lock_recovery()
2837 qla82xx_rom_unlock(ha); in qla82xx_rom_lock_recovery()
2857 struct qla_hw_data *ha = vha->hw; in qla82xx_device_bootstrap() local
2860 need_reset = qla82xx_need_reset(ha); in qla82xx_device_bootstrap()
2864 if (ha->flags.isp82xx_fw_hung) in qla82xx_device_bootstrap()
2865 qla82xx_rom_lock_recovery(ha); in qla82xx_device_bootstrap()
2867 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); in qla82xx_device_bootstrap()
2870 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); in qla82xx_device_bootstrap()
2876 qla82xx_rom_lock_recovery(ha); in qla82xx_device_bootstrap()
2882 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING); in qla82xx_device_bootstrap()
2884 qla82xx_idc_unlock(ha); in qla82xx_device_bootstrap()
2886 qla82xx_idc_lock(ha); in qla82xx_device_bootstrap()
2891 qla82xx_clear_drv_active(ha); in qla82xx_device_bootstrap()
2892 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED); in qla82xx_device_bootstrap()
2899 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY); in qla82xx_device_bootstrap()
2917 struct qla_hw_data *ha = vha->hw; in qla82xx_need_qsnt_handler() local
2927 qla82xx_set_qsnt_ready(ha); in qla82xx_need_qsnt_handler()
2932 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_need_qsnt_handler()
2933 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_need_qsnt_handler()
2947 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, in qla82xx_need_qsnt_handler()
2951 qla82xx_idc_unlock(ha); in qla82xx_need_qsnt_handler()
2953 qla82xx_idc_lock(ha); in qla82xx_need_qsnt_handler()
2959 qla82xx_idc_unlock(ha); in qla82xx_need_qsnt_handler()
2961 qla82xx_idc_lock(ha); in qla82xx_need_qsnt_handler()
2963 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_need_qsnt_handler()
2964 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_need_qsnt_handler()
2967 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); in qla82xx_need_qsnt_handler()
2972 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT); in qla82xx_need_qsnt_handler()
2989 struct qla_hw_data *ha = vha->hw; in qla82xx_wait_for_state_change() local
2994 qla82xx_idc_lock(ha); in qla82xx_wait_for_state_change()
2995 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); in qla82xx_wait_for_state_change()
2996 qla82xx_idc_unlock(ha); in qla82xx_wait_for_state_change()
3005 struct qla_hw_data *ha = vha->hw; in qla8xxx_dev_failed_handler() local
3011 if (IS_QLA82XX(ha)) { in qla8xxx_dev_failed_handler()
3012 qla82xx_clear_drv_active(ha); in qla8xxx_dev_failed_handler()
3013 qla82xx_idc_unlock(ha); in qla8xxx_dev_failed_handler()
3014 } else if (IS_QLA8044(ha)) { in qla8xxx_dev_failed_handler()
3015 qla8044_clear_drv_active(ha); in qla8xxx_dev_failed_handler()
3016 qla8044_idc_unlock(ha); in qla8xxx_dev_failed_handler()
3044 struct qla_hw_data *ha = vha->hw; in qla82xx_need_reset_handler() local
3045 struct req_que *req = ha->req_q_map[0]; in qla82xx_need_reset_handler()
3048 qla82xx_idc_unlock(ha); in qla82xx_need_reset_handler()
3050 ha->isp_ops->get_flash_version(vha, req->ring); in qla82xx_need_reset_handler()
3051 ha->isp_ops->nvram_config(vha); in qla82xx_need_reset_handler()
3052 qla82xx_idc_lock(ha); in qla82xx_need_reset_handler()
3055 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_need_reset_handler()
3056 if (!ha->flags.nic_core_reset_owner) { in qla82xx_need_reset_handler()
3058 "reset_acknowledged by 0x%x\n", ha->portnum); in qla82xx_need_reset_handler()
3059 qla82xx_set_rst_ready(ha); in qla82xx_need_reset_handler()
3061 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); in qla82xx_need_reset_handler()
3068 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); in qla82xx_need_reset_handler()
3070 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_need_reset_handler()
3071 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_need_reset_handler()
3072 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); in qla82xx_need_reset_handler()
3086 qla82xx_idc_unlock(ha); in qla82xx_need_reset_handler()
3088 qla82xx_idc_lock(ha); in qla82xx_need_reset_handler()
3089 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); in qla82xx_need_reset_handler()
3090 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); in qla82xx_need_reset_handler()
3091 if (ha->flags.nic_core_reset_owner) in qla82xx_need_reset_handler()
3093 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); in qla82xx_need_reset_handler()
3111 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); in qla82xx_need_reset_handler()
3112 qla82xx_set_rst_ready(ha); in qla82xx_need_reset_handler()
3126 struct qla_hw_data *ha = vha->hw; in qla82xx_check_md_needed() local
3130 fw_major_version = ha->fw_major_version; in qla82xx_check_md_needed()
3131 fw_minor_version = ha->fw_minor_version; in qla82xx_check_md_needed()
3132 fw_subminor_version = ha->fw_subminor_version; in qla82xx_check_md_needed()
3139 if (!ha->fw_dumped) { in qla82xx_check_md_needed()
3140 if ((fw_major_version != ha->fw_major_version || in qla82xx_check_md_needed()
3141 fw_minor_version != ha->fw_minor_version || in qla82xx_check_md_needed()
3142 fw_subminor_version != ha->fw_subminor_version) || in qla82xx_check_md_needed()
3143 (ha->prev_minidump_failed)) { in qla82xx_check_md_needed()
3148 ha->fw_major_version, in qla82xx_check_md_needed()
3149 ha->fw_minor_version, in qla82xx_check_md_needed()
3150 ha->fw_subminor_version, in qla82xx_check_md_needed()
3151 ha->prev_minidump_failed); in qla82xx_check_md_needed()
3214 struct qla_hw_data *ha = vha->hw; in qla82xx_device_state_handler() local
3217 qla82xx_idc_lock(ha); in qla82xx_device_state_handler()
3223 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); in qla82xx_device_state_handler()
3231 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); in qla82xx_device_state_handler()
3241 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); in qla82xx_device_state_handler()
3256 ha->flags.nic_core_reset_owner = 0; in qla82xx_device_state_handler()
3262 qla82xx_idc_unlock(ha); in qla82xx_device_state_handler()
3264 qla82xx_idc_lock(ha); in qla82xx_device_state_handler()
3270 qla82xx_idc_unlock(ha); in qla82xx_device_state_handler()
3272 qla82xx_idc_lock(ha); in qla82xx_device_state_handler()
3275 (ha->fcoe_dev_init_timeout * HZ); in qla82xx_device_state_handler()
3280 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ in qla82xx_device_state_handler()
3287 if (ha->flags.quiesce_owner) in qla82xx_device_state_handler()
3290 qla82xx_idc_unlock(ha); in qla82xx_device_state_handler()
3292 qla82xx_idc_lock(ha); in qla82xx_device_state_handler()
3295 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\ in qla82xx_device_state_handler()
3303 qla82xx_idc_unlock(ha); in qla82xx_device_state_handler()
3305 qla82xx_idc_lock(ha); in qla82xx_device_state_handler()
3310 qla82xx_idc_unlock(ha); in qla82xx_device_state_handler()
3318 struct qla_hw_data *ha = vha->hw; in qla82xx_check_temp() local
3320 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE); in qla82xx_check_temp()
3349 struct qla_hw_data *ha = vha->hw; in qla82xx_clear_pending_mbx() local
3351 if (ha->flags.mbox_busy) { in qla82xx_clear_pending_mbx()
3352 ha->flags.mbox_int = 1; in qla82xx_clear_pending_mbx()
3353 ha->flags.mbox_busy = 0; in qla82xx_clear_pending_mbx()
3356 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) in qla82xx_clear_pending_mbx()
3357 complete(&ha->mbx_intr_comp); in qla82xx_clear_pending_mbx()
3364 struct qla_hw_data *ha = vha->hw; in qla82xx_watchdog() local
3367 if (!ha->flags.nic_core_reset_hdlr_active) { in qla82xx_watchdog()
3368 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); in qla82xx_watchdog()
3371 ha->flags.isp82xx_fw_hung = 1; in qla82xx_watchdog()
3389 ha->flags.isp82xx_fw_hung = 1; in qla82xx_watchdog()
3395 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, in qla82xx_watchdog()
3397 halt_status = qla82xx_rd_32(ha, in qla82xx_watchdog()
3405 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), in qla82xx_watchdog()
3406 qla82xx_rd_32(ha, in qla82xx_watchdog()
3408 qla82xx_rd_32(ha, in qla82xx_watchdog()
3410 qla82xx_rd_32(ha, in qla82xx_watchdog()
3412 qla82xx_rd_32(ha, in qla82xx_watchdog()
3414 qla82xx_rd_32(ha, in qla82xx_watchdog()
3430 ha->flags.isp82xx_fw_hung = 1; in qla82xx_watchdog()
3441 struct qla_hw_data *ha = vha->hw; in qla82xx_load_risc() local
3443 if (IS_QLA82XX(ha)) in qla82xx_load_risc()
3445 else if (IS_QLA8044(ha)) { in qla82xx_load_risc()
3446 qla8044_idc_lock(ha); in qla82xx_load_risc()
3449 qla8044_idc_unlock(ha); in qla82xx_load_risc()
3458 struct qla_hw_data *ha = vha->hw; in qla82xx_set_reset_owner() local
3461 if (IS_QLA82XX(ha)) in qla82xx_set_reset_owner()
3462 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); in qla82xx_set_reset_owner()
3463 else if (IS_QLA8044(ha)) in qla82xx_set_reset_owner()
3469 if (IS_QLA82XX(ha)) { in qla82xx_set_reset_owner()
3470 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, in qla82xx_set_reset_owner()
3472 ha->flags.nic_core_reset_owner = 1; in qla82xx_set_reset_owner()
3474 "reset_owner is 0x%x\n", ha->portnum); in qla82xx_set_reset_owner()
3475 } else if (IS_QLA8044(ha)) in qla82xx_set_reset_owner()
3499 struct qla_hw_data *ha = vha->hw; in qla82xx_abort_isp() local
3506 ha->flags.nic_core_reset_hdlr_active = 1; in qla82xx_abort_isp()
3508 qla82xx_idc_lock(ha); in qla82xx_abort_isp()
3510 qla82xx_idc_unlock(ha); in qla82xx_abort_isp()
3512 if (IS_QLA82XX(ha)) in qla82xx_abort_isp()
3514 else if (IS_QLA8044(ha)) { in qla82xx_abort_isp()
3515 qla8044_idc_lock(ha); in qla82xx_abort_isp()
3518 qla8044_idc_unlock(ha); in qla82xx_abort_isp()
3522 qla82xx_idc_lock(ha); in qla82xx_abort_isp()
3523 qla82xx_clear_rst_ready(ha); in qla82xx_abort_isp()
3524 qla82xx_idc_unlock(ha); in qla82xx_abort_isp()
3527 ha->flags.isp82xx_fw_hung = 0; in qla82xx_abort_isp()
3528 ha->flags.nic_core_reset_hdlr_active = 0; in qla82xx_abort_isp()
3535 if (ha->isp_abort_cnt == 0) { in qla82xx_abort_isp()
3543 ha->isp_ops->reset_adapter(vha); in qla82xx_abort_isp()
3549 ha->isp_abort_cnt--; in qla82xx_abort_isp()
3552 ha->isp_abort_cnt); in qla82xx_abort_isp()
3556 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; in qla82xx_abort_isp()
3559 ha->isp_abort_cnt); in qla82xx_abort_isp()
3642 struct qla_hw_data *ha = vha->hw; in qla82xx_chip_reset_cleanup() local
3648 if (!ha->flags.isp82xx_fw_hung) { in qla82xx_chip_reset_cleanup()
3651 if (IS_QLA82XX(ha)) in qla82xx_chip_reset_cleanup()
3653 else if (IS_QLA8044(ha)) in qla82xx_chip_reset_cleanup()
3656 ha->flags.isp82xx_fw_hung = 1; in qla82xx_chip_reset_cleanup()
3664 __func__, ha->flags.isp82xx_fw_hung); in qla82xx_chip_reset_cleanup()
3667 if (!ha->flags.isp82xx_fw_hung) { in qla82xx_chip_reset_cleanup()
3672 spin_lock_irqsave(&ha->hardware_lock, flags); in qla82xx_chip_reset_cleanup()
3673 for (que = 0; que < ha->max_req_queues; que++) { in qla82xx_chip_reset_cleanup()
3674 req = ha->req_q_map[que]; in qla82xx_chip_reset_cleanup()
3683 !ha->flags.isp82xx_fw_hung) { in qla82xx_chip_reset_cleanup()
3685 &ha->hardware_lock, flags); in qla82xx_chip_reset_cleanup()
3686 if (ha->isp_ops->abort_command(sp)) { in qla82xx_chip_reset_cleanup()
3695 spin_lock_irqsave(&ha->hardware_lock, flags); in qla82xx_chip_reset_cleanup()
3700 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla82xx_chip_reset_cleanup()
3717 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_control() local
3726 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; in qla82xx_minidump_process_control()
3733 qla82xx_md_rw_32(ha, crb_addr, in qla82xx_minidump_process_control()
3739 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3740 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); in qla82xx_minidump_process_control()
3745 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3752 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); in qla82xx_minidump_process_control()
3756 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3758 qla82xx_md_rw_32(ha, crb_addr, read_value, 1); in qla82xx_minidump_process_control()
3765 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3776 read_value = qla82xx_md_rw_32(ha, in qla82xx_minidump_process_control()
3789 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_control()
3809 qla82xx_md_rw_32(ha, addr, read_value, 1); in qla82xx_minidump_process_control()
3834 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_rdocm() local
3846 (r_addr + ha->nx_pcibase)); in qla82xx_minidump_process_rdocm()
3857 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_rdmux() local
3870 qla82xx_md_rw_32(ha, s_addr, s_value, 1); in qla82xx_minidump_process_rdmux()
3871 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_rdmux()
3883 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_rdcrb() local
3894 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_rdcrb()
3906 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_l2tag() local
3928 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); in qla82xx_minidump_process_l2tag()
3930 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); in qla82xx_minidump_process_l2tag()
3935 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); in qla82xx_minidump_process_l2tag()
3951 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_l2tag()
3965 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_l1cache() local
3983 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); in qla82xx_minidump_process_l1cache()
3984 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); in qla82xx_minidump_process_l1cache()
3987 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_l1cache()
4000 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_queue() local
4014 qla82xx_md_rw_32(ha, s_addr, qid, 1); in qla82xx_minidump_process_queue()
4017 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_queue()
4030 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_rdrom() local
4041 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, in qla82xx_minidump_process_rdrom()
4043 r_value = qla82xx_md_rw_32(ha, in qla82xx_minidump_process_rdrom()
4056 struct qla_hw_data *ha = vha->hw; in qla82xx_minidump_process_rdmem() local
4085 write_lock_irqsave(&ha->hw_lock, flags); in qla82xx_minidump_process_rdmem()
4087 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); in qla82xx_minidump_process_rdmem()
4089 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); in qla82xx_minidump_process_rdmem()
4091 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); in qla82xx_minidump_process_rdmem()
4093 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); in qla82xx_minidump_process_rdmem()
4096 r_value = qla82xx_md_rw_32(ha, in qla82xx_minidump_process_rdmem()
4105 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_minidump_process_rdmem()
4110 r_data = qla82xx_md_rw_32(ha, in qla82xx_minidump_process_rdmem()
4116 write_unlock_irqrestore(&ha->hw_lock, flags); in qla82xx_minidump_process_rdmem()
4124 struct qla_hw_data *ha = vha->hw; in qla82xx_validate_template_chksum() local
4126 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; in qla82xx_validate_template_chksum()
4127 int count = ha->md_template_size/sizeof(uint32_t); in qla82xx_validate_template_chksum()
4151 struct qla_hw_data *ha = vha->hw; in qla82xx_md_collect() local
4159 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; in qla82xx_md_collect()
4160 data_ptr = (uint32_t *)ha->md_dump; in qla82xx_md_collect()
4162 if (ha->fw_dumped) { in qla82xx_md_collect()
4165 "-- ignoring request.\n", ha->fw_dump); in qla82xx_md_collect()
4169 ha->fw_dumped = 0; in qla82xx_md_collect()
4171 if (!ha->md_tmplt_hdr || !ha->md_dump) { in qla82xx_md_collect()
4177 if (ha->flags.isp82xx_no_md_cap) { in qla82xx_md_collect()
4181 ha->flags.isp82xx_no_md_cap = 0; in qla82xx_md_collect()
4214 total_data_size = ha->md_dump_size; in qla82xx_md_collect()
4228 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); in qla82xx_md_collect()
4261 data_collected, (ha->md_dump_size - data_collected)); in qla82xx_md_collect()
4332 (uint8_t *)ha->md_dump; in qla82xx_md_collect()
4348 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); in qla82xx_md_collect()
4349 ha->fw_dumped = 1; in qla82xx_md_collect()
4359 struct qla_hw_data *ha = vha->hw; in qla82xx_md_alloc() local
4363 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; in qla82xx_md_alloc()
4374 ha->md_dump_size += tmplt_hdr->capture_size_array[k]; in qla82xx_md_alloc()
4377 if (ha->md_dump) { in qla82xx_md_alloc()
4383 ha->md_dump = vmalloc(ha->md_dump_size); in qla82xx_md_alloc()
4384 if (ha->md_dump == NULL) { in qla82xx_md_alloc()
4387 "(0x%x).\n", ha->md_dump_size); in qla82xx_md_alloc()
4396 struct qla_hw_data *ha = vha->hw; in qla82xx_md_free() local
4399 if (ha->md_tmplt_hdr) { in qla82xx_md_free()
4402 ha->md_tmplt_hdr, ha->md_template_size / 1024); in qla82xx_md_free()
4403 dma_free_coherent(&ha->pdev->dev, ha->md_template_size, in qla82xx_md_free()
4404 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); in qla82xx_md_free()
4405 ha->md_tmplt_hdr = NULL; in qla82xx_md_free()
4409 if (ha->md_dump) { in qla82xx_md_free()
4412 ha->md_dump, ha->md_dump_size / 1024); in qla82xx_md_free()
4413 vfree(ha->md_dump); in qla82xx_md_free()
4414 ha->md_dump_size = 0; in qla82xx_md_free()
4415 ha->md_dump = NULL; in qla82xx_md_free()
4422 struct qla_hw_data *ha = vha->hw; in qla82xx_md_prep() local
4430 ha->md_template_size / 1024); in qla82xx_md_prep()
4433 if (IS_QLA8044(ha)) in qla82xx_md_prep()
4447 ha->md_dump_size / 1024); in qla82xx_md_prep()
4451 ha->md_tmplt_hdr, in qla82xx_md_prep()
4452 ha->md_template_size / 1024); in qla82xx_md_prep()
4453 dma_free_coherent(&ha->pdev->dev, in qla82xx_md_prep()
4454 ha->md_template_size, in qla82xx_md_prep()
4455 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); in qla82xx_md_prep()
4456 ha->md_tmplt_hdr = NULL; in qla82xx_md_prep()
4468 struct qla_hw_data *ha = vha->hw; in qla82xx_beacon_on() local
4469 qla82xx_idc_lock(ha); in qla82xx_beacon_on()
4477 ha->beacon_blink_led = 1; in qla82xx_beacon_on()
4479 qla82xx_idc_unlock(ha); in qla82xx_beacon_on()
4488 struct qla_hw_data *ha = vha->hw; in qla82xx_beacon_off() local
4489 qla82xx_idc_lock(ha); in qla82xx_beacon_off()
4497 ha->beacon_blink_led = 0; in qla82xx_beacon_off()
4499 qla82xx_idc_unlock(ha); in qla82xx_beacon_off()
4506 struct qla_hw_data *ha = vha->hw; in qla82xx_fw_dump() local
4508 if (!ha->allow_cna_fw_dump) in qla82xx_fw_dump()
4512 ha->flags.isp82xx_no_md_cap = 1; in qla82xx_fw_dump()
4513 qla82xx_idc_lock(ha); in qla82xx_fw_dump()
4515 qla82xx_idc_unlock(ha); in qla82xx_fw_dump()