Lines Matching refs:ha
35 struct qla_hw_data *ha; in qla2100_intr_handler() local
51 ha = rsp->hw; in qla2100_intr_handler()
52 reg = &ha->iobase->isp; in qla2100_intr_handler()
55 spin_lock_irqsave(&ha->hardware_lock, flags); in qla2100_intr_handler()
56 vha = pci_get_drvdata(ha->pdev); in qla2100_intr_handler()
62 if (pci_channel_offline(ha->pdev)) in qla2100_intr_handler()
73 ha->isp_ops->fw_dump(vha, 1); in qla2100_intr_handler()
84 mb[0] = RD_MAILBOX_REG(ha, reg, 0); in qla2100_intr_handler()
89 mb[1] = RD_MAILBOX_REG(ha, reg, 1); in qla2100_intr_handler()
90 mb[2] = RD_MAILBOX_REG(ha, reg, 2); in qla2100_intr_handler()
91 mb[3] = RD_MAILBOX_REG(ha, reg, 3); in qla2100_intr_handler()
109 qla2x00_handle_mbx_completion(ha, status); in qla2100_intr_handler()
110 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla2100_intr_handler()
161 struct qla_hw_data *ha; in qla2300_intr_handler() local
171 ha = rsp->hw; in qla2300_intr_handler()
172 reg = &ha->iobase->isp; in qla2300_intr_handler()
175 spin_lock_irqsave(&ha->hardware_lock, flags); in qla2300_intr_handler()
176 vha = pci_get_drvdata(ha->pdev); in qla2300_intr_handler()
182 if (unlikely(pci_channel_offline(ha->pdev))) in qla2300_intr_handler()
204 ha->isp_ops->fw_dump(vha, 1); in qla2300_intr_handler()
223 mb[1] = RD_MAILBOX_REG(ha, reg, 1); in qla2300_intr_handler()
224 mb[2] = RD_MAILBOX_REG(ha, reg, 2); in qla2300_intr_handler()
225 mb[3] = RD_MAILBOX_REG(ha, reg, 3); in qla2300_intr_handler()
239 mb[2] = RD_MAILBOX_REG(ha, reg, 2); in qla2300_intr_handler()
250 qla2x00_handle_mbx_completion(ha, status); in qla2300_intr_handler()
251 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla2300_intr_handler()
267 struct qla_hw_data *ha = vha->hw; in qla2x00_mbx_completion() local
268 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_mbx_completion()
271 mboxes = (1 << ha->mbx_count) - 1; in qla2x00_mbx_completion()
272 if (!ha->mcp) in qla2x00_mbx_completion()
275 mboxes = ha->mcp->in_mb; in qla2x00_mbx_completion()
278 ha->flags.mbox_int = 1; in qla2x00_mbx_completion()
279 ha->mailbox_out[0] = mb0; in qla2x00_mbx_completion()
281 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1); in qla2x00_mbx_completion()
283 for (cnt = 1; cnt < ha->mbx_count; cnt++) { in qla2x00_mbx_completion()
284 if (IS_QLA2200(ha) && cnt == 8) in qla2x00_mbx_completion()
285 wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8); in qla2x00_mbx_completion()
287 ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr); in qla2x00_mbx_completion()
289 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla2x00_mbx_completion()
359 qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed) in qla2x00_get_link_speed_str() argument
366 if (IS_QLA2100(ha) || IS_QLA2200(ha)) in qla2x00_get_link_speed_str()
379 struct qla_hw_data *ha = vha->hw; in qla83xx_handle_8200_aen() local
401 ha->flags.nic_core_hung = 1; in qla83xx_handle_8200_aen()
532 if (ha->flags.nic_core_reset_owner) in qla83xx_handle_8200_aen()
541 struct qla_hw_data *ha = vha->hw; in qla2x00_is_a_vp_did() local
547 if (!ha->num_vhosts) in qla2x00_is_a_vp_did()
550 spin_lock_irqsave(&ha->vport_slock, flags); in qla2x00_is_a_vp_did()
551 list_for_each_entry(vp, &ha->vp_list, list) { in qla2x00_is_a_vp_did()
558 spin_unlock_irqrestore(&ha->vport_slock, flags); in qla2x00_is_a_vp_did()
574 struct qla_hw_data *ha = vha->hw; in qla2x00_async_event() local
575 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_async_event()
576 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; in qla2x00_async_event()
577 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; in qla2x00_async_event()
584 if (IS_CNA_CAPABLE(ha)) in qla2x00_async_event()
613 handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6); in qla2x00_async_event()
621 handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6); in qla2x00_async_event()
622 handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7); in qla2x00_async_event()
629 ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) | in qla2x00_async_event()
630 RD_MAILBOX_REG(ha, reg, 6)); in qla2x00_async_event()
656 mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? in qla2x00_async_event()
662 ha->isp_ops->fw_dump(vha, 1); in qla2x00_async_event()
664 if (IS_FWI2_CAPABLE(ha)) { in qla2x00_async_event()
673 if ((mbx & MBX_3) && (ha->port_no == 0)) in qla2x00_async_event()
731 if (IS_QLA2100(ha) || IS_QLA2200(ha)) in qla2x00_async_event()
732 ha->link_data_rate = PORT_SPEED_1GB; in qla2x00_async_event()
734 ha->link_data_rate = mb[1]; in qla2x00_async_event()
738 qla2x00_get_link_speed_str(ha, ha->link_data_rate)); in qla2x00_async_event()
741 qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate); in qla2x00_async_event()
745 mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha)) in qla2x00_async_event()
747 mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(®82->mailbox_out[4]) in qla2x00_async_event()
762 if (ha->flags.fawwpn_enabled) { in qla2x00_async_event()
763 void *wwpn = ha->init_cb->port_name; in qla2x00_async_event()
786 ha->link_data_rate = PORT_SPEED_UNKNOWN; in qla2x00_async_event()
807 ha->operating_mode = LOOP; in qla2x00_async_event()
814 if (IS_QLA2100(ha)) in qla2x00_async_event()
817 if (IS_CNA_CAPABLE(ha)) { in qla2x00_async_event()
821 if (ha->notify_dcbx_comp && !vha->vp_idx) in qla2x00_async_event()
822 complete(&ha->dcbx_comp); in qla2x00_async_event()
851 ha->flags.gpsc_supported = 1; in qla2x00_async_event()
856 if (IS_QLA2100(ha)) in qla2x00_async_event()
895 if (IS_QLA2XXX_MIDTYPE(ha) && in qla2x00_async_event()
924 ha->link_data_rate = PORT_SPEED_UNKNOWN; in qla2x00_async_event()
970 if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff)) in qla2x00_async_event()
1021 if (IS_FWI2_CAPABLE(ha)) in qla2x00_async_event()
1043 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); in qla2x00_async_event()
1051 ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2]; in qla2x00_async_event()
1054 ha->cs84xx->op_fw_version); in qla2x00_async_event()
1057 ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2]; in qla2x00_async_event()
1060 ha->cs84xx->diag_fw_version); in qla2x00_async_event()
1063 ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2]; in qla2x00_async_event()
1064 ha->cs84xx->fw_update = 1; in qla2x00_async_event()
1067 ha->cs84xx->gold_fw_version); in qla2x00_async_event()
1074 spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags); in qla2x00_async_event()
1092 if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { in qla2x00_async_event()
1108 if (ha->notify_lb_portup_comp && !vha->vp_idx) in qla2x00_async_event()
1109 complete(&ha->lb_portup_comp); in qla2x00_async_event()
1113 IS_QLA8044(ha)) in qla2x00_async_event()
1141 if (!vha->vp_idx && ha->num_vhosts) in qla2x00_async_event()
1155 struct qla_hw_data *ha = vha->hw; in qla2x00_process_completed_request() local
1162 if (IS_P3P_TYPE(ha)) in qla2x00_process_completed_request()
1175 sp->done(ha, sp, DID_OK << 16); in qla2x00_process_completed_request()
1179 if (IS_P3P_TYPE(ha)) in qla2x00_process_completed_request()
1190 struct qla_hw_data *ha = vha->hw; in qla2x00_get_sp_from_handle() local
1199 if (IS_P3P_TYPE(ha)) in qla2x00_get_sp_from_handle()
1602 struct qla_hw_data *ha = rsp->hw; in qla2x00_process_response_queue() local
1603 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_process_response_queue()
1608 vha = pci_get_drvdata(ha->pdev); in qla2x00_process_response_queue()
1672 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index); in qla2x00_process_response_queue()
1852 struct qla_hw_data *ha = vha->hw; in qla25xx_process_bidir_status_iocb() local
1886 if (IS_FWI2_CAPABLE(ha)) { in qla25xx_process_bidir_status_iocb()
2015 struct qla_hw_data *ha = vha->hw; in qla2x00_status_entry() local
2026 if (IS_FWI2_CAPABLE(ha)) { in qla2x00_status_entry()
2036 req = ha->req_q_map[que]; in qla2x00_status_entry()
2040 que >= find_first_zero_bit(ha->req_qid_map, ha->max_req_queues)) { in qla2x00_status_entry()
2058 if (IS_P3P_TYPE(ha)) in qla2x00_status_entry()
2102 if (IS_FWI2_CAPABLE(ha)) { in qla2x00_status_entry()
2133 if (IS_FWI2_CAPABLE(ha)) { in qla2x00_status_entry()
2148 if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE && in qla2x00_status_entry()
2207 resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len; in qla2x00_status_entry()
2210 if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) { in qla2x00_status_entry()
2294 if (IS_FWI2_CAPABLE(ha)) in qla2x00_status_entry()
2323 if (!IS_PI_SPLIT_DET_CAPABLE(ha)) in qla2x00_status_entry()
2350 sp->done(ha, sp, res); in qla2x00_status_entry()
2364 struct qla_hw_data *ha = rsp->hw; in qla2x00_status_cont_entry() local
2365 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev); in qla2x00_status_cont_entry()
2392 if (IS_FWI2_CAPABLE(ha)) in qla2x00_status_cont_entry()
2407 sp->done(ha, sp, cp->result); in qla2x00_status_cont_entry()
2420 struct qla_hw_data *ha = vha->hw; in qla2x00_error_entry() local
2429 if (que >= ha->max_req_queues || !ha->req_q_map[que]) in qla2x00_error_entry()
2432 req = ha->req_q_map[que]; in qla2x00_error_entry()
2439 sp->done(ha, sp, res); in qla2x00_error_entry()
2446 if (IS_P3P_TYPE(ha)) in qla2x00_error_entry()
2464 struct qla_hw_data *ha = vha->hw; in qla24xx_mbx_completion() local
2465 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_mbx_completion()
2468 mboxes = (1 << ha->mbx_count) - 1; in qla24xx_mbx_completion()
2469 if (!ha->mcp) in qla24xx_mbx_completion()
2472 mboxes = ha->mcp->in_mb; in qla24xx_mbx_completion()
2475 ha->flags.mbox_int = 1; in qla24xx_mbx_completion()
2476 ha->mailbox_out[0] = mb0; in qla24xx_mbx_completion()
2480 for (cnt = 1; cnt < ha->mbx_count; cnt++) { in qla24xx_mbx_completion()
2482 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla24xx_mbx_completion()
2514 struct qla_hw_data *ha = vha->hw; in qla24xx_process_response_queue() local
2594 if (IS_P3P_TYPE(ha)) { in qla24xx_process_response_queue()
2595 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; in qla24xx_process_response_queue()
2606 struct qla_hw_data *ha = vha->hw; in qla2xxx_check_risc_status() local
2607 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla2xxx_check_risc_status()
2609 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && in qla2xxx_check_risc_status()
2610 !IS_QLA27XX(ha)) in qla2xxx_check_risc_status()
2664 struct qla_hw_data *ha; in qla24xx_intr_handler() local
2681 ha = rsp->hw; in qla24xx_intr_handler()
2682 reg = &ha->iobase->isp24; in qla24xx_intr_handler()
2685 if (unlikely(pci_channel_offline(ha->pdev))) in qla24xx_intr_handler()
2688 spin_lock_irqsave(&ha->hardware_lock, flags); in qla24xx_intr_handler()
2689 vha = pci_get_drvdata(ha->pdev); in qla24xx_intr_handler()
2695 if (unlikely(pci_channel_offline(ha->pdev))) in qla24xx_intr_handler()
2706 ha->isp_ops->fw_dump(vha, 1); in qla24xx_intr_handler()
2746 if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1))) in qla24xx_intr_handler()
2749 qla2x00_handle_mbx_completion(ha, status); in qla24xx_intr_handler()
2750 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla24xx_intr_handler()
2758 struct qla_hw_data *ha; in qla24xx_msix_rsp_q() local
2771 ha = rsp->hw; in qla24xx_msix_rsp_q()
2772 reg = &ha->iobase->isp24; in qla24xx_msix_rsp_q()
2774 spin_lock_irqsave(&ha->hardware_lock, flags); in qla24xx_msix_rsp_q()
2776 vha = pci_get_drvdata(ha->pdev); in qla24xx_msix_rsp_q()
2785 if (!ha->flags.disable_msix_handshake) { in qla24xx_msix_rsp_q()
2790 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla24xx_msix_rsp_q()
2798 struct qla_hw_data *ha; in qla25xx_msix_rsp_q() local
2811 ha = rsp->hw; in qla25xx_msix_rsp_q()
2812 vha = pci_get_drvdata(ha->pdev); in qla25xx_msix_rsp_q()
2815 if (!ha->flags.disable_msix_handshake) { in qla25xx_msix_rsp_q()
2816 reg = &ha->iobase->isp24; in qla25xx_msix_rsp_q()
2817 spin_lock_irqsave(&ha->hardware_lock, flags); in qla25xx_msix_rsp_q()
2820 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla25xx_msix_rsp_q()
2824 queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work); in qla25xx_msix_rsp_q()
2834 struct qla_hw_data *ha; in qla24xx_msix_default() local
2849 ha = rsp->hw; in qla24xx_msix_default()
2850 reg = &ha->iobase->isp24; in qla24xx_msix_default()
2853 spin_lock_irqsave(&ha->hardware_lock, flags); in qla24xx_msix_default()
2854 vha = pci_get_drvdata(ha->pdev); in qla24xx_msix_default()
2860 if (unlikely(pci_channel_offline(ha->pdev))) in qla24xx_msix_default()
2871 ha->isp_ops->fw_dump(vha, 1); in qla24xx_msix_default()
2911 qla2x00_handle_mbx_completion(ha, status); in qla24xx_msix_default()
2912 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla24xx_msix_default()
2942 qla24xx_disable_msix(struct qla_hw_data *ha) in qla24xx_disable_msix() argument
2946 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla24xx_disable_msix()
2948 for (i = 0; i < ha->msix_count; i++) { in qla24xx_disable_msix()
2949 qentry = &ha->msix_entries[i]; in qla24xx_disable_msix()
2953 pci_disable_msix(ha->pdev); in qla24xx_disable_msix()
2954 kfree(ha->msix_entries); in qla24xx_disable_msix()
2955 ha->msix_entries = NULL; in qla24xx_disable_msix()
2956 ha->flags.msix_enabled = 0; in qla24xx_disable_msix()
2962 qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp) in qla24xx_enable_msix() argument
2969 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla24xx_enable_msix()
2971 entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count, in qla24xx_enable_msix()
2979 for (i = 0; i < ha->msix_count; i++) in qla24xx_enable_msix()
2982 ret = pci_enable_msix_range(ha->pdev, in qla24xx_enable_msix()
2983 entries, MIN_MSIX_COUNT, ha->msix_count); in qla24xx_enable_msix()
2988 ha->msix_count, ret); in qla24xx_enable_msix()
2990 } else if (ret < ha->msix_count) { in qla24xx_enable_msix()
2994 ha->msix_count, ret, ret); in qla24xx_enable_msix()
2995 ha->msix_count = ret; in qla24xx_enable_msix()
2996 ha->max_rsp_queues = ha->msix_count - 1; in qla24xx_enable_msix()
2998 ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) * in qla24xx_enable_msix()
2999 ha->msix_count, GFP_KERNEL); in qla24xx_enable_msix()
3000 if (!ha->msix_entries) { in qla24xx_enable_msix()
3006 ha->flags.msix_enabled = 1; in qla24xx_enable_msix()
3008 for (i = 0; i < ha->msix_count; i++) { in qla24xx_enable_msix()
3009 qentry = &ha->msix_entries[i]; in qla24xx_enable_msix()
3018 qentry = &ha->msix_entries[i]; in qla24xx_enable_msix()
3019 if (IS_P3P_TYPE(ha)) in qla24xx_enable_msix()
3038 if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) { in qla24xx_enable_msix()
3039 qentry = &ha->msix_entries[ATIO_VECTOR]; in qla24xx_enable_msix()
3053 qla24xx_disable_msix(ha); in qla24xx_enable_msix()
3054 ha->mqenable = 0; in qla24xx_enable_msix()
3059 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { in qla24xx_enable_msix()
3060 if (ha->msixbase && ha->mqiobase && in qla24xx_enable_msix()
3061 (ha->max_rsp_queues > 1 || ha->max_req_queues > 1)) in qla24xx_enable_msix()
3062 ha->mqenable = 1; in qla24xx_enable_msix()
3064 if (ha->mqiobase in qla24xx_enable_msix()
3065 && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1)) in qla24xx_enable_msix()
3066 ha->mqenable = 1; in qla24xx_enable_msix()
3069 ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues); in qla24xx_enable_msix()
3072 ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues); in qla24xx_enable_msix()
3080 qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp) in qla2x00_request_irqs() argument
3083 device_reg_t *reg = ha->iobase; in qla2x00_request_irqs()
3084 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla2x00_request_irqs()
3087 if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) && in qla2x00_request_irqs()
3088 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha) && in qla2x00_request_irqs()
3089 !IS_QLA27XX(ha)) in qla2x00_request_irqs()
3092 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && in qla2x00_request_irqs()
3093 (ha->pdev->subsystem_device == 0x7040 || in qla2x00_request_irqs()
3094 ha->pdev->subsystem_device == 0x7041 || in qla2x00_request_irqs()
3095 ha->pdev->subsystem_device == 0x1705)) { in qla2x00_request_irqs()
3098 ha->pdev->subsystem_vendor, in qla2x00_request_irqs()
3099 ha->pdev->subsystem_device); in qla2x00_request_irqs()
3103 if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) { in qla2x00_request_irqs()
3106 ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX); in qla2x00_request_irqs()
3110 ret = qla24xx_enable_msix(ha, rsp); in qla2x00_request_irqs()
3114 ha->chip_revision, ha->fw_attributes); in qla2x00_request_irqs()
3123 if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) && in qla2x00_request_irqs()
3124 !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha) && in qla2x00_request_irqs()
3125 !IS_QLA27XX(ha)) in qla2x00_request_irqs()
3128 ret = pci_enable_msi(ha->pdev); in qla2x00_request_irqs()
3132 ha->flags.msi_enabled = 1; in qla2x00_request_irqs()
3139 if (!ha->flags.msi_enabled && IS_QLA82XX(ha)) in qla2x00_request_irqs()
3142 ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler, in qla2x00_request_irqs()
3143 ha->flags.msi_enabled ? 0 : IRQF_SHARED, in qla2x00_request_irqs()
3148 ha->pdev->irq); in qla2x00_request_irqs()
3150 } else if (!ha->flags.msi_enabled) { in qla2x00_request_irqs()
3153 ha->flags.mr_intr_valid = 1; in qla2x00_request_irqs()
3157 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha)) in qla2x00_request_irqs()
3160 spin_lock_irq(&ha->hardware_lock); in qla2x00_request_irqs()
3162 spin_unlock_irq(&ha->hardware_lock); in qla2x00_request_irqs()
3171 struct qla_hw_data *ha = vha->hw; in qla2x00_free_irqs() local
3178 if (!ha->rsp_q_map || !ha->rsp_q_map[0]) in qla2x00_free_irqs()
3180 rsp = ha->rsp_q_map[0]; in qla2x00_free_irqs()
3182 if (ha->flags.msix_enabled) in qla2x00_free_irqs()
3183 qla24xx_disable_msix(ha); in qla2x00_free_irqs()
3184 else if (ha->flags.msi_enabled) { in qla2x00_free_irqs()
3185 free_irq(ha->pdev->irq, rsp); in qla2x00_free_irqs()
3186 pci_disable_msi(ha->pdev); in qla2x00_free_irqs()
3188 free_irq(ha->pdev->irq, rsp); in qla2x00_free_irqs()
3194 struct qla_hw_data *ha = rsp->hw; in qla25xx_request_irq() local
3197 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla25xx_request_irq()