Lines Matching refs:uint32_t
107 uint32_t firmware_options_1;
108 uint32_t firmware_options_2;
109 uint32_t firmware_options_3;
172 uint32_t host_p;
203 uint32_t efi_parameters;
263 uint32_t checksum;
298 uint32_t request_q_address[2];
299 uint32_t response_q_address[2];
300 uint32_t prio_request_q_address[2];
308 uint32_t atio_q_address[2];
332 uint32_t firmware_options_1;
353 uint32_t firmware_options_2;
379 uint32_t firmware_options_3;
395 uint32_t handle; /* System handle. */
412 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
416 uint32_t rd_byte_count; /* Total Byte count Read. */
417 uint32_t wr_byte_count; /* Total Byte count write. */
422 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
433 uint32_t handle; /* System handle. */
451 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
453 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
455 uint32_t byte_count; /* Total byte count. */
460 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
461 uint32_t fcp_data_dseg_len; /* Data segment length. */
471 uint32_t handle; /* System handle. */
502 uint32_t byte_count; /* Total byte count. */
507 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
508 uint32_t dseg_0_len; /* Data segment 0 length. */
519 uint32_t handle; /* System handle. */
533 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
535 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
537 uint32_t byte_count; /* Total byte count. */
542 uint32_t crc_context_address[2]; /* Data segment address. */
558 uint32_t handle; /* System handle. */
563 uint32_t residual_len; /* FW calc residual transfer length. */
574 uint32_t rsp_residual_count; /* FCP RSP residual count. */
576 uint32_t sense_len; /* FCP SENSE length. */
577 uint32_t rsp_data_len; /* FCP response data length. */
613 uint32_t handle; /* System handle. */
642 uint32_t handle; /* System handle. */
660 uint32_t rsp_byte_count;
661 uint32_t cmd_byte_count;
663 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
664 uint32_t dseg_0_len; /* Data segment 0 length. */
665 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
666 uint32_t dseg_1_len; /* Data segment 1 length. */
679 uint32_t handle; /* System handle. */
692 uint32_t rx_xchg_address; /* Receive exchange address. */
712 uint32_t rx_byte_count;
713 uint32_t tx_byte_count;
715 uint32_t tx_address[2]; /* Data segment 0 address. */
716 uint32_t tx_len; /* Data segment 0 length. */
717 uint32_t rx_address[2]; /* Data segment 1 address. */
718 uint32_t rx_len; /* Data segment 1 length. */
727 uint32_t handle; /* System handle. */
738 uint32_t rx_xchg_address; /* Receive exchange address. */
750 uint32_t total_byte_count;
751 uint32_t error_subcode_1;
752 uint32_t error_subcode_2;
764 uint32_t handle; /* System handle. */
777 uint32_t handle; /* System handle. */
812 uint32_t io_parameter[11]; /* General I/O parameters. */
838 uint32_t handle; /* System handle. */
850 uint32_t control_flags; /* Control Flags. */
873 uint32_t handle; /* System handle. */
881 uint32_t handle_to_abort; /* System handle to abort. */
896 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
947 uint32_t flash_data; /* Flash/NVRAM BIOS data. */
949 uint32_t ctrl_status; /* Control/Status. */
975 uint32_t ictrl; /* Interrupt control. */
978 uint32_t istatus; /* Interrupt status. */
981 uint32_t unused_1[2]; /* Gap. */
984 uint32_t req_q_in; /* In-Pointer. */
985 uint32_t req_q_out; /* Out-Pointer. */
987 uint32_t rsp_q_in; /* In-Pointer. */
988 uint32_t rsp_q_out; /* Out-Pointer. */
990 uint32_t preq_q_in; /* In-Pointer. */
991 uint32_t preq_q_out; /* Out-Pointer. */
993 uint32_t unused_2[2]; /* Gap. */
996 uint32_t atio_q_in; /* In-Pointer. */
997 uint32_t atio_q_out; /* Out-Pointer. */
999 uint32_t host_status;
1003 uint32_t hccr; /* Host command & control register. */
1025 uint32_t gpiod; /* GPIO Data register. */
1044 uint32_t gpioe; /* GPIO Enable register. */
1052 uint32_t iobase_addr; /* I/O Bus Base Address register. */
1054 uint32_t unused_3[10]; /* Gap. */
1089 uint32_t iobase_window;
1090 uint32_t iobase_c4;
1091 uint32_t iobase_c8;
1092 uint32_t unused_4_1[6]; /* Gap. */
1093 uint32_t iobase_q;
1094 uint32_t unused_5[2]; /* Gap. */
1095 uint32_t iobase_select;
1096 uint32_t unused_6[2]; /* Gap. */
1097 uint32_t iobase_sdata;
1196 uint32_t handle; /* System handle. */
1232 uint32_t handle; /* System handle. */
1279 uint32_t handle; /* System handle. */
1301 uint32_t handle; /* System handle. */
1307 uint32_t exch_addr;
1311 uint32_t io_parameter_0;
1312 uint32_t io_parameter_1;
1313 uint32_t tx_address[2]; /* Data segment 0 address. */
1314 uint32_t tx_len; /* Data segment 0 length. */
1315 uint32_t rx_address[2]; /* Data segment 1 address. */
1316 uint32_t rx_len; /* Data segment 1 length. */
1340 uint32_t block_size;
1341 uint32_t alt_block_size;
1342 uint32_t flash_size;
1343 uint32_t wrt_enable_data;
1397 uint32_t code;
1398 uint32_t size;
1399 uint32_t start;
1400 uint32_t end;
1446 uint32_t handle;
1461 uint32_t fw_ver;
1462 uint32_t exchange_address;
1464 uint32_t reserved_3[3];
1465 uint32_t fw_size;
1466 uint32_t fw_seq_size;
1467 uint32_t relative_offset;
1469 uint32_t dseg_address[2];
1470 uint32_t dseg_length;
1479 uint32_t handle;
1493 uint32_t fw_ver;
1494 uint32_t exchange_address;
1496 uint32_t reserved_2[6];
1506 uint32_t handle;
1519 uint32_t parameter1;
1520 uint32_t parameter2;
1521 uint32_t parameter3;
1523 uint32_t reserved3[3];
1524 uint32_t total_byte_cnt;
1525 uint32_t reserved4;
1527 uint32_t dseg_address[2];
1528 uint32_t dseg_length;
1537 uint32_t handle;
1541 uint32_t residual_count;
1543 uint32_t reserved[12];
1605 uint32_t firmware_options_1;
1606 uint32_t firmware_options_2;
1607 uint32_t firmware_options_3;
1662 uint32_t host_p;
1693 uint32_t efi_parameters;
1749 uint32_t checksum;
1784 uint32_t request_q_address[2];
1785 uint32_t response_q_address[2];
1786 uint32_t prio_request_q_address[2];
1792 uint32_t atio_q_address[2];
1808 uint32_t firmware_options_1;
1826 uint32_t firmware_options_2;
1847 uint32_t firmware_options_3;
1899 uint32_t src_pid; /* Src port id. high order byte */
1901 uint32_t dst_pid; /* Src port id. high order byte */