Lines Matching refs:uint32_t
98 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
100 #define LSD(x) ((uint32_t)((uint64_t)(x)))
101 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
103 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
294 uint32_t request_sense_length;
295 uint32_t fw_sense_length;
331 uint32_t flags;
332 uint32_t data;
343 uint32_t req_len;
344 uint32_t rsp_len;
362 uint32_t cmd_hndl;
390 uint32_t handle;
427 uint32_t transfer_size;
428 uint32_t iteration_count;
484 uint32_t host_status;
587 uint32_t req_q_in;
588 uint32_t req_q_out;
589 uint32_t rsp_q_in;
590 uint32_t rsp_q_out;
591 uint32_t atio_q_in;
592 uint32_t atio_q_out;
597 uint32_t mailbox0; /* 00 */
598 uint32_t mailbox1; /* 04 */
599 uint32_t mailbox2; /* 08 */
600 uint32_t mailbox3; /* 0C */
601 uint32_t mailbox4; /* 10 */
602 uint32_t mailbox5; /* 14 */
603 uint32_t mailbox6; /* 18 */
604 uint32_t mailbox7; /* 1C */
605 uint32_t mailbox8; /* 20 */
606 uint32_t mailbox9; /* 24 */
607 uint32_t mailbox10; /* 28 */
608 uint32_t mailbox11;
609 uint32_t mailbox12;
610 uint32_t mailbox13;
611 uint32_t mailbox14;
612 uint32_t mailbox15;
613 uint32_t mailbox16;
614 uint32_t mailbox17;
615 uint32_t mailbox18;
616 uint32_t mailbox19;
617 uint32_t mailbox20;
618 uint32_t mailbox21;
619 uint32_t mailbox22;
620 uint32_t mailbox23;
621 uint32_t mailbox24;
622 uint32_t mailbox25;
623 uint32_t mailbox26;
624 uint32_t mailbox27;
625 uint32_t mailbox28;
626 uint32_t mailbox29;
627 uint32_t mailbox30;
628 uint32_t mailbox31;
629 uint32_t aenmailbox0;
630 uint32_t aenmailbox1;
631 uint32_t aenmailbox2;
632 uint32_t aenmailbox3;
633 uint32_t aenmailbox4;
634 uint32_t aenmailbox5;
635 uint32_t aenmailbox6;
636 uint32_t aenmailbox7;
638 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
639 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
641 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
642 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
644 uint32_t initval0; /* B0 */
645 uint32_t initval1; /* B4 */
646 uint32_t initval2; /* B8 */
647 uint32_t initval3; /* BC */
648 uint32_t initval4; /* C0 */
649 uint32_t initval5; /* C4 */
650 uint32_t initval6; /* C8 */
651 uint32_t initval7; /* CC */
652 uint32_t fwheartbeat; /* D0 */
653 uint32_t pseudoaen; /* D4 */
707 uint32_t out_mb; /* outbound from driver */
708 uint32_t in_mb; /* Incoming from RISC */
712 uint32_t tov;
720 uint32_t out_mb; /* outbound from driver */
721 uint32_t in_mb; /* Incoming from RISC */
722 uint32_t mb[MAILBOX_REGISTER_COUNT];
725 uint32_t tov;
1160 uint32_t request_q_address[2];
1161 uint32_t response_q_address[2];
1224 uint32_t link_fail_cnt;
1225 uint32_t loss_sync_cnt;
1226 uint32_t loss_sig_cnt;
1227 uint32_t prim_seq_err_cnt;
1228 uint32_t inval_xmit_word_cnt;
1229 uint32_t inval_crc_cnt;
1230 uint32_t lip_cnt;
1231 uint32_t unused1[0x1a];
1232 uint32_t tx_frames;
1233 uint32_t rx_frames;
1234 uint32_t discarded_frames;
1235 uint32_t dropped_frames;
1236 uint32_t unused2[1];
1237 uint32_t nos_rcvd;
1501 uint32_t handle; /* System defined handle */
1503 uint32_t signature;
1514 uint32_t signature;
1543 uint32_t handle; /* System handle. */
1556 uint32_t byte_count; /* Total byte count. */
1557 uint32_t dseg_0_address; /* Data segment 0 address. */
1558 uint32_t dseg_0_length; /* Data segment 0 length. */
1559 uint32_t dseg_1_address; /* Data segment 1 address. */
1560 uint32_t dseg_1_length; /* Data segment 1 length. */
1561 uint32_t dseg_2_address; /* Data segment 2 address. */
1562 uint32_t dseg_2_length; /* Data segment 2 length. */
1574 uint32_t handle; /* System handle. */
1582 uint32_t byte_count; /* Total byte count. */
1583 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1584 uint32_t dseg_0_length; /* Data segment 0 length. */
1585 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1586 uint32_t dseg_1_length; /* Data segment 1 length. */
1598 uint32_t reserved;
1599 uint32_t dseg_0_address; /* Data segment 0 address. */
1600 uint32_t dseg_0_length; /* Data segment 0 length. */
1601 uint32_t dseg_1_address; /* Data segment 1 address. */
1602 uint32_t dseg_1_length; /* Data segment 1 length. */
1603 uint32_t dseg_2_address; /* Data segment 2 address. */
1604 uint32_t dseg_2_length; /* Data segment 2 length. */
1605 uint32_t dseg_3_address; /* Data segment 3 address. */
1606 uint32_t dseg_3_length; /* Data segment 3 length. */
1607 uint32_t dseg_4_address; /* Data segment 4 address. */
1608 uint32_t dseg_4_length; /* Data segment 4 length. */
1609 uint32_t dseg_5_address; /* Data segment 5 address. */
1610 uint32_t dseg_5_length; /* Data segment 5 length. */
1611 uint32_t dseg_6_address; /* Data segment 6 address. */
1612 uint32_t dseg_6_length; /* Data segment 6 length. */
1624 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1625 uint32_t dseg_0_length; /* Data segment 0 length. */
1626 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1627 uint32_t dseg_1_length; /* Data segment 1 length. */
1628 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1629 uint32_t dseg_2_length; /* Data segment 2 length. */
1630 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1631 uint32_t dseg_3_length; /* Data segment 3 length. */
1632 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1633 uint32_t dseg_4_length; /* Data segment 4 length. */
1659 uint32_t handle; /* System handle. */
1673 uint32_t reserved_1;
1676 uint32_t reserved_4;
1677 uint32_t data_address[2];
1678 uint32_t data_length;
1679 uint32_t reserved_5[2];
1680 uint32_t reserved_6;
1687 uint32_t reserved_2;
1688 uint32_t data_address[2];
1689 uint32_t data_length;
1690 uint32_t dif_address[2];
1691 uint32_t dif_length; /* Data segment 0
1716 uint32_t handle; /* System handle. */
1723 uint32_t residual_length; /* Residual transfer length. */
1819 uint32_t handle[15]; /* System handles. */
1844 uint32_t sys_define_2; /* System defined. */
1868 uint32_t handle1; /* System handle. */
1880 uint32_t handle2;
1881 uint32_t rsp_bytecount;
1882 uint32_t req_bytecount;
1883 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1884 uint32_t dseg_req_length; /* Data segment 0 length. */
1885 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1886 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1909 uint32_t handle;
1916 uint32_t sys_define2[2];
1926 uint32_t reserved_2[2];
1942 uint32_t b24 : 24;
2014 uint32_t flags;
2175 uint32_t max_ct_len;
2180 uint32_t count;
2198 uint32_t max_ct_len;
2200 uint32_t vendor_id;
2201 uint32_t num_ports;
2209 uint32_t count;
2253 uint32_t sup_speed;
2254 uint32_t cur_speed;
2255 uint32_t max_frame_size;
2261 uint32_t port_type;
2262 uint32_t port_supported_cos;
2265 uint32_t port_state;
2266 uint32_t num_ports;
2267 uint32_t port_id;
2275 uint32_t count;
2284 uint32_t sup_speed;
2285 uint32_t cur_speed;
2286 uint32_t max_frame_size;
2293 uint32_t count;
2384 uint32_t entry_count;
2391 uint32_t entry_count;
2496 uint32_t entry_count;
2560 uint32_t buffer_address[2];
2565 uint32_t reserved_3;
2580 uint32_t segs[4];
2608 uint32_t options;
2636 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2655 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2656 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2657 uint32_t);
2660 uint32_t, uint32_t);
2661 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2662 uint32_t);
2671 uint32_t, uint32_t);
2672 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2673 uint32_t);
2700 uint32_t vector;
2747 uint32_t evtcode;
2748 uint32_t mbx[8];
2749 uint32_t count;
2764 uint32_t fw_update;
2765 uint32_t op_fw_version;
2766 uint32_t op_fw_size;
2767 uint32_t op_fw_seq_size;
2768 uint32_t diag_fw_version;
2769 uint32_t gold_fw_version;
2773 uint32_t total_isp_aborts;
2778 uint32_t control_requests;
2781 uint32_t stat_max_pend_cmds;
2782 uint32_t stat_max_qfull_cmds_alloc;
2783 uint32_t stat_max_qfull_cmds_dropped;
2811 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2812 uint32_t __iomem *rsp_q_out;
2838 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2839 uint32_t __iomem *req_q_out;
2852 uint32_t current_outstanding_cmd;
2866 uint32_t len;
2878 uint32_t enable_class_2:1;
2879 uint32_t enable_explicit_conf:1;
2880 uint32_t ini_mode_force_reverse:1;
2881 uint32_t node_name_set:1;
2888 uint32_t __iomem *atio_q_in;
2889 uint32_t __iomem *atio_q_out;
2899 uint32_t saved_firmware_options_1;
2900 uint32_t saved_firmware_options_2;
2901 uint32_t saved_firmware_options_3;
2908 uint32_t num_pend_cmds;
2909 uint32_t num_qfull_cmds_alloc;
2910 uint32_t num_qfull_cmds_dropped;
2912 uint32_t leak_exchg_thresh_hold;
2932 uint32_t mbox_int :1;
2933 uint32_t mbox_busy :1;
2934 uint32_t disable_risc_code_load :1;
2935 uint32_t enable_64bit_addressing :1;
2936 uint32_t enable_lip_reset :1;
2937 uint32_t enable_target_reset :1;
2938 uint32_t enable_lip_full_login :1;
2939 uint32_t enable_led_scheme :1;
2941 uint32_t msi_enabled :1;
2942 uint32_t msix_enabled :1;
2943 uint32_t disable_serdes :1;
2944 uint32_t gpsc_supported :1;
2945 uint32_t npiv_supported :1;
2946 uint32_t pci_channel_io_perm_failure :1;
2947 uint32_t fce_enabled :1;
2948 uint32_t fac_supported :1;
2950 uint32_t chip_reset_done :1;
2951 uint32_t running_gold_fw :1;
2952 uint32_t eeh_busy :1;
2953 uint32_t cpu_affinity_enabled :1;
2954 uint32_t disable_msix_handshake :1;
2955 uint32_t fcp_prio_enabled :1;
2956 uint32_t isp82xx_fw_hung:1;
2957 uint32_t nic_core_hung:1;
2959 uint32_t quiesce_owner:1;
2960 uint32_t nic_core_reset_hdlr_active:1;
2961 uint32_t nic_core_reset_owner:1;
2962 uint32_t isp82xx_no_md_cap:1;
2963 uint32_t host_shutting_down:1;
2964 uint32_t idc_compl_status:1;
2966 uint32_t mr_reset_hdlr_active:1;
2967 uint32_t mr_intr_valid:1;
2968 uint32_t fawwpn_enabled:1;
2993 uint32_t rqstq_intr_code;
2994 uint32_t mbx_intr_code;
2995 uint32_t req_que_len;
2996 uint32_t rsp_que_len;
2997 uint32_t req_que_off;
2998 uint32_t rsp_que_off;
3055 uint32_t isp_abort_cnt;
3065 uint32_t device_type;
3193 uint32_t login_retry_count;
3240 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3241 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3272 uint32_t fw_memory_size;
3273 uint32_t fw_transfer_size;
3274 uint32_t fw_srisc_address;
3281 uint32_t fw_shared_ram_start;
3282 uint32_t fw_shared_ram_end;
3289 uint32_t mpi_capabilities;
3294 uint32_t fw_dump_template_len;
3297 uint32_t fw_dump_len;
3318 uint32_t chain_offset;
3323 uint32_t fce_bufs;
3328 uint32_t pci_attr;
3340 uint32_t optrom_size;
3345 uint32_t optrom_region_start;
3346 uint32_t optrom_region_size;
3356 uint32_t fw_revision[4];
3358 uint32_t gold_fw_version[4];
3361 uint32_t flash_conf_off;
3362 uint32_t flash_data_off;
3363 uint32_t nvram_conf_off;
3364 uint32_t nvram_data_off;
3366 uint32_t fdt_wrt_disable;
3367 uint32_t fdt_wrt_enable;
3368 uint32_t fdt_erase_cmd;
3369 uint32_t fdt_block_size;
3370 uint32_t fdt_unprotect_sec_cmd;
3371 uint32_t fdt_protect_sec_cmd;
3372 uint32_t fdt_wrt_sts_reg_cmd;
3374 uint32_t flt_region_flt;
3375 uint32_t flt_region_fdt;
3376 uint32_t flt_region_boot;
3377 uint32_t flt_region_fw;
3378 uint32_t flt_region_vpd_nvram;
3379 uint32_t flt_region_vpd;
3380 uint32_t flt_region_nvram;
3381 uint32_t flt_region_npiv_conf;
3382 uint32_t flt_region_gold_fw;
3383 uint32_t flt_region_fcp_prio;
3384 uint32_t flt_region_bootload;
3427 uint32_t crb_win;
3428 uint32_t curr_window;
3429 uint32_t ddr_mn_window;
3433 uint32_t fcoe_dev_init_timeout;
3434 uint32_t fcoe_reset_timeout;
3449 uint32_t md_template_size;
3453 uint32_t md_dump_size;
3458 uint32_t idc_audit_ts;
3459 uint32_t idc_extend_tmo;
3472 uint32_t chip_reset;
3493 uint32_t init_done :1;
3494 uint32_t online :1;
3495 uint32_t reset_active :1;
3497 uint32_t management_server_logged_in :1;
3498 uint32_t process_response_queue :1;
3499 uint32_t difdix_supported:1;
3500 uint32_t delete_progress:1;
3502 uint32_t fw_tgt_reported:1;
3547 uint32_t device_flags;
3573 uint32_t timer_active;
3594 uint32_t vp_abort_cnt;