Lines Matching defs:qla_hw_data
2925 struct qla_hw_data { struct
2926 struct pci_dev *pdev;
2929 mempool_t *srb_mempool;
2931 volatile struct {
2970 } flags;
2979 spinlock_t hardware_lock ____cacheline_aligned;
2980 int bars;
2981 int mem_only;
2982 device_reg_t *iobase; /* Base I/O address */
2983 resource_size_t pio_address;
2986 dma_addr_t bar0_hdl;
2988 void __iomem *cregbase;
2989 dma_addr_t bar2_hdl;
2993 uint32_t rqstq_intr_code;
2994 uint32_t mbx_intr_code;
2995 uint32_t req_que_len;
2996 uint32_t rsp_que_len;
2997 uint32_t req_que_off;
2998 uint32_t rsp_que_off;
3001 device_reg_t *mqiobase;
3002 device_reg_t *msixbase;
3003 uint16_t msix_count;
3004 uint8_t mqenable;
3005 struct req_que **req_q_map;
3006 struct rsp_que **rsp_q_map;
3007 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3008 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3009 uint8_t max_req_queues;
3010 uint8_t max_rsp_queues;
3011 struct qla_npiv_entry *npiv_info;
3012 uint16_t nvram_npiv_size;
3014 uint16_t switch_cap;
3020 uint8_t port_no; /* Physical port of adapter */
3023 uint8_t loop_down_abort_time; /* port down timer */
3024 atomic_t loop_down_timer; /* loop down timer */
3025 uint8_t link_down_timeout; /* link down timeout */
3026 uint16_t max_loop_id;
3027 uint16_t max_fibre_devices; /* Maximum number of targets */
3029 uint16_t fb_rev;
3030 uint16_t min_external_loopid; /* First external loop Id */
3040 uint16_t link_data_rate; /* F/W operating speed */
3042 uint8_t current_topology;
3043 uint8_t prev_topology;
3049 uint8_t operating_mode; /* F/W operating mode */
3054 uint8_t interrupts_on;
3055 uint32_t isp_abort_cnt;
3065 uint32_t device_type;
3171 uint8_t serial0;
3172 uint8_t serial1;
3173 uint8_t serial2;
3178 uint16_t nvram_size;
3179 uint16_t nvram_base;
3180 void *nvram;
3181 uint16_t vpd_size;
3182 uint16_t vpd_base;
3183 void *vpd;
3185 uint16_t loop_reset_delay;
3186 uint8_t retry_count;
3187 uint8_t login_timeout;
3188 uint16_t r_a_tov;
3189 int port_down_retry_count;
3190 uint8_t mbx_count;
3191 uint8_t aen_mbx_count;
3193 uint32_t login_retry_count;
3195 ms_iocb_entry_t *ms_iocb;
3196 dma_addr_t ms_iocb_dma;
3197 struct ct_sns_pkt *ct_sns;
3198 dma_addr_t ct_sns_dma;
3200 struct sns_cmd_pkt *sns_cmd;
3201 dma_addr_t sns_cmd_dma;
3205 void *sfp_data;
3206 dma_addr_t sfp_data_dma;
3209 void *xgmac_data;
3210 dma_addr_t xgmac_data_dma;
3213 void *dcbx_tlv;
3214 dma_addr_t dcbx_tlv_dma;
3216 struct task_struct *dpc_thread;
3217 uint8_t dpc_active; /* DPC routine is active */
3219 dma_addr_t gid_list_dma;
3220 struct gid_list_info *gid_list;
3221 int gid_list_info_size;
3225 struct dma_pool *s_dma_pool;
3227 dma_addr_t init_cb_dma;
3228 init_cb_t *init_cb;
3229 int init_cb_size;
3230 dma_addr_t ex_init_cb_dma;
3231 struct ex_init_cb_81xx *ex_init_cb;
3233 void *async_pd;
3234 dma_addr_t async_pd_dma;
3236 void *swl;
3239 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3240 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3241 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3243 mbx_cmd_t *mcp;
3244 struct mbx_cmd_32 *mcp32;
3246 unsigned long mbx_cmd_flags;
3251 struct mutex vport_lock; /* Virtual port synchronization */
3252 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3253 struct completion mbx_cmd_comp; /* Serialize mbx access */
3254 struct completion mbx_intr_comp; /* Used for completion notification */
3255 struct completion dcbx_comp; /* For set port config notification */
3256 struct completion lb_portup_comp; /* Used to wait for link up during
3261 int notify_dcbx_comp;
3262 int notify_lb_portup_comp;
3263 struct mutex selflogin_lock;
3266 uint16_t fw_major_version;
3267 uint16_t fw_minor_version;
3268 uint16_t fw_subminor_version;
3269 uint16_t fw_attributes;
3270 uint16_t fw_attributes_h;
3271 uint16_t fw_attributes_ext[2];
3272 uint32_t fw_memory_size;
3273 uint32_t fw_transfer_size;
3274 uint32_t fw_srisc_address;
3278 uint16_t fw_xcb_count;
3279 uint16_t fw_iocb_count;
3281 uint32_t fw_shared_ram_start;
3282 uint32_t fw_shared_ram_end;
3284 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3285 uint8_t fw_seriallink_options[4];
3286 uint16_t fw_seriallink_options24[4];
3288 uint8_t mpi_version[3];
3289 uint32_t mpi_capabilities;
3290 uint8_t phy_version[3];
3293 void *fw_dump_template;
3294 uint32_t fw_dump_template_len;
3296 struct qla2xxx_fw_dump *fw_dump;
3297 uint32_t fw_dump_len;
3298 int fw_dumped;
3299 unsigned long fw_dump_cap_flags;
3308 int fw_dump_reading;
3309 int prev_minidump_failed;
3310 dma_addr_t eft_dma;
3311 void *eft;
3314 dma_addr_t mctp_dump_dma;
3315 void *mctp_dump;
3316 int mctp_dumped;
3317 int mctp_dump_reading;
3318 uint32_t chain_offset;
3319 struct dentry *dfs_dir;
3320 struct dentry *dfs_fce;
3321 dma_addr_t fce_dma;
3322 void *fce;
3323 uint32_t fce_bufs;
3324 uint16_t fce_mb[8];
3325 uint64_t fce_wr, fce_rd;
3326 struct mutex fce_mutex;
3328 uint32_t pci_attr;
3329 uint16_t chip_revision;
3331 uint16_t product_id[4];
3333 uint8_t model_number[16+1];
3335 char model_desc[80];
3336 uint8_t adapter_id[16+1];
3339 char *optrom_buffer;
3340 uint32_t optrom_size;
3341 int optrom_state;
3345 uint32_t optrom_region_start;
3346 uint32_t optrom_region_size;
3347 struct mutex optrom_mutex;
3353 uint8_t bios_revision[2];
3354 uint8_t efi_revision[2];
3355 uint8_t fcode_revision[16];
3356 uint32_t fw_revision[4];
3358 uint32_t gold_fw_version[4];
3361 uint32_t flash_conf_off;
3362 uint32_t flash_data_off;
3363 uint32_t nvram_conf_off;
3364 uint32_t nvram_data_off;
3366 uint32_t fdt_wrt_disable;
3367 uint32_t fdt_wrt_enable;
3368 uint32_t fdt_erase_cmd;
3369 uint32_t fdt_block_size;
3370 uint32_t fdt_unprotect_sec_cmd;
3371 uint32_t fdt_protect_sec_cmd;
3372 uint32_t fdt_wrt_sts_reg_cmd;
3374 uint32_t flt_region_flt;
3375 uint32_t flt_region_fdt;
3376 uint32_t flt_region_boot;
3377 uint32_t flt_region_fw;
3378 uint32_t flt_region_vpd_nvram;
3379 uint32_t flt_region_vpd;
3380 uint32_t flt_region_nvram;
3381 uint32_t flt_region_npiv_conf;
3382 uint32_t flt_region_gold_fw;
3383 uint32_t flt_region_fcp_prio;
3384 uint32_t flt_region_bootload;
3387 uint16_t beacon_blink_led;
3388 uint8_t beacon_color_state;
3394 uint16_t zio_mode;
3395 uint16_t zio_timer;
3397 struct qla_msix_entry *msix_entries;
3399 struct list_head vp_list; /* list of VP */
3400 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3402 uint16_t num_vhosts; /* number of vports created */
3403 uint16_t num_vsans; /* number of vsan created */
3404 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
3405 int cur_vport_count;
3407 struct qla_chip_state_84xx *cs84xx;
3408 struct qla_statistics qla_stats;
3409 struct isp_operations *isp_ops;
3410 struct workqueue_struct *wq;
3411 struct qlfc_fw fw_buf;
3414 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3416 struct dma_pool *dl_dma_pool;
3419 struct dma_pool *fcp_cmnd_dma_pool;
3420 mempool_t *ctx_mempool;
3423 unsigned long nx_pcibase; /* Base I/O address */
3424 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
3425 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
3427 uint32_t crb_win;
3428 uint32_t curr_window;
3429 uint32_t ddr_mn_window;
3430 unsigned long mn_win_crb;
3431 unsigned long ms_win_crb;
3432 int qdr_sn_window;
3433 uint32_t fcoe_dev_init_timeout;
3434 uint32_t fcoe_reset_timeout;
3435 rwlock_t hw_lock;
3436 uint16_t portnum; /* port number */
3437 int link_width;
3438 struct fw_blob *hablob;
3439 struct qla82xx_legacy_intr_set nx_legacy_intr;
3441 uint16_t gbl_dsd_inuse;
3442 uint16_t gbl_dsd_avail;
3443 struct list_head gbl_dsd_list;
3446 uint8_t fw_type;
3447 __le32 file_prd_off; /* File firmware product offset */
3449 uint32_t md_template_size;
3450 void *md_tmplt_hdr;
3451 dma_addr_t md_tmplt_hdr_dma;
3452 void *md_dump;
3453 uint32_t md_dump_size;
3455 void *loop_id_map;
3458 uint32_t idc_audit_ts;
3459 uint32_t idc_extend_tmo;
3462 struct workqueue_struct *dpc_lp_wq;
3463 struct work_struct idc_aen;
3465 struct workqueue_struct *dpc_hp_wq;
3466 struct work_struct nic_core_reset;
3467 struct work_struct idc_state_handler;
3468 struct work_struct nic_core_unrecoverable;
3469 struct work_struct board_disable;
3471 struct mr_data_fx00 mr;
3472 uint32_t chip_reset;
3474 struct qlt_hw_data tgt;
3475 int allow_cna_fw_dump;