Lines Matching refs:uint32_t
59 uint32_t host_status;
60 uint32_t host_reg[32];
61 uint32_t shadow_reg[7];
63 uint32_t xseq_gp_reg[128];
64 uint32_t xseq_0_reg[16];
65 uint32_t xseq_1_reg[16];
66 uint32_t rseq_gp_reg[128];
67 uint32_t rseq_0_reg[16];
68 uint32_t rseq_1_reg[16];
69 uint32_t rseq_2_reg[16];
70 uint32_t cmd_dma_reg[16];
71 uint32_t req0_dma_reg[15];
72 uint32_t resp0_dma_reg[15];
73 uint32_t req1_dma_reg[15];
74 uint32_t xmt0_dma_reg[32];
75 uint32_t xmt1_dma_reg[32];
76 uint32_t xmt2_dma_reg[32];
77 uint32_t xmt3_dma_reg[32];
78 uint32_t xmt4_dma_reg[32];
79 uint32_t xmt_data_dma_reg[16];
80 uint32_t rcvt0_data_dma_reg[32];
81 uint32_t rcvt1_data_dma_reg[32];
82 uint32_t risc_gp_reg[128];
83 uint32_t lmc_reg[112];
84 uint32_t fpm_hdw_reg[192];
85 uint32_t fb_hdw_reg[176];
86 uint32_t code_ram[0x2000];
87 uint32_t ext_mem[1];
91 uint32_t host_status;
92 uint32_t host_risc_reg[32];
93 uint32_t pcie_regs[4];
94 uint32_t host_reg[32];
95 uint32_t shadow_reg[11];
96 uint32_t risc_io_reg;
98 uint32_t xseq_gp_reg[128];
99 uint32_t xseq_0_reg[48];
100 uint32_t xseq_1_reg[16];
101 uint32_t rseq_gp_reg[128];
102 uint32_t rseq_0_reg[32];
103 uint32_t rseq_1_reg[16];
104 uint32_t rseq_2_reg[16];
105 uint32_t aseq_gp_reg[128];
106 uint32_t aseq_0_reg[32];
107 uint32_t aseq_1_reg[16];
108 uint32_t aseq_2_reg[16];
109 uint32_t cmd_dma_reg[16];
110 uint32_t req0_dma_reg[15];
111 uint32_t resp0_dma_reg[15];
112 uint32_t req1_dma_reg[15];
113 uint32_t xmt0_dma_reg[32];
114 uint32_t xmt1_dma_reg[32];
115 uint32_t xmt2_dma_reg[32];
116 uint32_t xmt3_dma_reg[32];
117 uint32_t xmt4_dma_reg[32];
118 uint32_t xmt_data_dma_reg[16];
119 uint32_t rcvt0_data_dma_reg[32];
120 uint32_t rcvt1_data_dma_reg[32];
121 uint32_t risc_gp_reg[128];
122 uint32_t lmc_reg[128];
123 uint32_t fpm_hdw_reg[192];
124 uint32_t fb_hdw_reg[192];
125 uint32_t code_ram[0x2000];
126 uint32_t ext_mem[1];
130 uint32_t host_status;
131 uint32_t host_risc_reg[32];
132 uint32_t pcie_regs[4];
133 uint32_t host_reg[32];
134 uint32_t shadow_reg[11];
135 uint32_t risc_io_reg;
137 uint32_t xseq_gp_reg[128];
138 uint32_t xseq_0_reg[48];
139 uint32_t xseq_1_reg[16];
140 uint32_t rseq_gp_reg[128];
141 uint32_t rseq_0_reg[32];
142 uint32_t rseq_1_reg[16];
143 uint32_t rseq_2_reg[16];
144 uint32_t aseq_gp_reg[128];
145 uint32_t aseq_0_reg[32];
146 uint32_t aseq_1_reg[16];
147 uint32_t aseq_2_reg[16];
148 uint32_t cmd_dma_reg[16];
149 uint32_t req0_dma_reg[15];
150 uint32_t resp0_dma_reg[15];
151 uint32_t req1_dma_reg[15];
152 uint32_t xmt0_dma_reg[32];
153 uint32_t xmt1_dma_reg[32];
154 uint32_t xmt2_dma_reg[32];
155 uint32_t xmt3_dma_reg[32];
156 uint32_t xmt4_dma_reg[32];
157 uint32_t xmt_data_dma_reg[16];
158 uint32_t rcvt0_data_dma_reg[32];
159 uint32_t rcvt1_data_dma_reg[32];
160 uint32_t risc_gp_reg[128];
161 uint32_t lmc_reg[128];
162 uint32_t fpm_hdw_reg[224];
163 uint32_t fb_hdw_reg[208];
164 uint32_t code_ram[0x2000];
165 uint32_t ext_mem[1];
169 uint32_t host_status;
170 uint32_t host_risc_reg[48];
171 uint32_t pcie_regs[4];
172 uint32_t host_reg[32];
173 uint32_t shadow_reg[11];
174 uint32_t risc_io_reg;
176 uint32_t xseq_gp_reg[256];
177 uint32_t xseq_0_reg[48];
178 uint32_t xseq_1_reg[16];
179 uint32_t xseq_2_reg[16];
180 uint32_t rseq_gp_reg[256];
181 uint32_t rseq_0_reg[32];
182 uint32_t rseq_1_reg[16];
183 uint32_t rseq_2_reg[16];
184 uint32_t rseq_3_reg[16];
185 uint32_t aseq_gp_reg[256];
186 uint32_t aseq_0_reg[32];
187 uint32_t aseq_1_reg[16];
188 uint32_t aseq_2_reg[16];
189 uint32_t aseq_3_reg[16];
190 uint32_t cmd_dma_reg[64];
191 uint32_t req0_dma_reg[15];
192 uint32_t resp0_dma_reg[15];
193 uint32_t req1_dma_reg[15];
194 uint32_t xmt0_dma_reg[32];
195 uint32_t xmt1_dma_reg[32];
196 uint32_t xmt2_dma_reg[32];
197 uint32_t xmt3_dma_reg[32];
198 uint32_t xmt4_dma_reg[32];
199 uint32_t xmt_data_dma_reg[16];
200 uint32_t rcvt0_data_dma_reg[32];
201 uint32_t rcvt1_data_dma_reg[32];
202 uint32_t risc_gp_reg[128];
203 uint32_t lmc_reg[128];
204 uint32_t fpm_hdw_reg[256];
205 uint32_t rq0_array_reg[256];
206 uint32_t rq1_array_reg[256];
207 uint32_t rp0_array_reg[256];
208 uint32_t rp1_array_reg[256];
209 uint32_t queue_control_reg[16];
210 uint32_t fb_hdw_reg[432];
211 uint32_t at0_array_reg[128];
212 uint32_t code_ram[0x2400];
213 uint32_t ext_mem[1];
226 uint32_t type;
227 uint32_t chain_size;
229 uint32_t size;
230 uint32_t addr_l;
231 uint32_t addr_h;
232 uint32_t eregs[8];
236 uint32_t type;
237 uint32_t chain_size;
239 uint32_t count;
240 uint32_t qregs[4 * QLA_MQ_SIZE];
244 uint32_t queue;
248 uint32_t number;
249 uint32_t size;
253 uint32_t type;
254 uint32_t chain_size;
265 uint32_t version;
267 uint32_t fw_major_version;
268 uint32_t fw_minor_version;
269 uint32_t fw_subminor_version;
270 uint32_t fw_attributes;
272 uint32_t vendor;
273 uint32_t device;
274 uint32_t subsystem_vendor;
275 uint32_t subsystem_device;
277 uint32_t fixed_size;
278 uint32_t mem_size;
279 uint32_t req_q_size;
280 uint32_t rsp_q_size;
282 uint32_t eft_size;
283 uint32_t eft_addr_l;
284 uint32_t eft_addr_h;
286 uint32_t header_size;
313 ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
315 ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
318 ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
320 ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
352 extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
353 uint32_t, void **);
354 extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *,
355 uint32_t, void **);