Lines Matching refs:u32
122 u32 tag_of_task_to_be_managed;
125 u32 signature;
156 u32 data_type;
159 u32 direct_len;
160 u32 direct_offset;
166 u32 direct_len;
170 u32 direct_len;
171 u32 direct_offset;
172 u32 read_len;
198 u32 (*is_our_interupt)(struct pm8001_hba_info *pm8001_ha);
212 struct pm8001_device *pm8001_dev, u32 flag);
213 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
215 u32 phy_id, u32 phy_op);
217 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
218 u32 cmd_tag);
226 struct pm8001_device *pm8001_dev, u32 state);
228 u32 state);
230 u32 state);
235 u32 encrypt;
236 u32 n_phy;
256 u32 phy_type;
258 u32 frame_rcvd_size;
269 u32 attached_phy;
270 u32 id;
273 u32 device_id;
274 u32 running_req;
292 u32 n_elem;
293 u32 ccb_tag;
304 u32 phys_addr_hi;
305 u32 phys_addr_lo;
306 u32 total_len;
307 u32 num_elements;
308 u32 element_size;
309 u32 alignment;
314 u32 count;
320 u32 cipher_mode;
321 u32 sec_mode;
322 u32 status;
323 u32 flag;
327 u32 phystart1_16[16];
328 u32 outbound_hw_event_pid1_16[16];
333 u32 signature;
334 u32 interface_rev;
335 u32 firmware_rev;
336 u32 max_out_io;
337 u32 max_sgl;
338 u32 ctrl_cap_flag;
339 u32 gst_offset;
340 u32 inbound_queue_offset;
341 u32 outbound_queue_offset;
342 u32 inbound_q_nppd_hppd;
343 u32 outbound_hw_event_pid0_3;
344 u32 outbound_hw_event_pid4_7;
345 u32 outbound_ncq_event_pid0_3;
346 u32 outbound_ncq_event_pid4_7;
347 u32 outbound_tgt_ITNexus_event_pid0_3;
348 u32 outbound_tgt_ITNexus_event_pid4_7;
349 u32 outbound_tgt_ssp_event_pid0_3;
350 u32 outbound_tgt_ssp_event_pid4_7;
351 u32 outbound_tgt_smp_event_pid0_3;
352 u32 outbound_tgt_smp_event_pid4_7;
353 u32 upper_event_log_addr;
354 u32 lower_event_log_addr;
355 u32 event_log_size;
356 u32 event_log_option;
357 u32 upper_iop_event_log_addr;
358 u32 lower_iop_event_log_addr;
359 u32 iop_event_log_size;
360 u32 iop_event_log_option;
361 u32 fatal_err_interrupt;
362 u32 fatal_err_dump_offset0;
363 u32 fatal_err_dump_length0;
364 u32 fatal_err_dump_offset1;
365 u32 fatal_err_dump_length1;
366 u32 hda_mode_flag;
367 u32 anolog_setup_table_offset;
368 u32 rsvd[4];
372 u32 signature;
373 u32 interface_rev;
374 u32 firmware_rev;
375 u32 max_out_io;
376 u32 max_sgl;
377 u32 ctrl_cap_flag;
378 u32 gst_offset;
379 u32 inbound_queue_offset;
380 u32 outbound_queue_offset;
381 u32 inbound_q_nppd_hppd;
382 u32 rsvd[8];
383 u32 crc_core_dump;
384 u32 rsvd1;
385 u32 upper_event_log_addr;
386 u32 lower_event_log_addr;
387 u32 event_log_size;
388 u32 event_log_severity;
389 u32 upper_pcs_event_log_addr;
390 u32 lower_pcs_event_log_addr;
391 u32 pcs_event_log_size;
392 u32 pcs_event_log_severity;
393 u32 fatal_err_interrupt;
394 u32 fatal_err_dump_offset0;
395 u32 fatal_err_dump_length0;
396 u32 fatal_err_dump_offset1;
397 u32 fatal_err_dump_length1;
398 u32 gpio_led_mapping;
399 u32 analog_setup_table_offset;
400 u32 int_vec_table_offset;
401 u32 phy_attr_table_offset;
402 u32 port_recovery_timer;
403 u32 interrupt_reassertion_delay;
404 u32 fatal_n_non_fatal_dump; /* 0x28 */
410 u32 gst_len_mpistate;
411 u32 iq_freeze_state0;
412 u32 iq_freeze_state1;
413 u32 msgu_tcnt;
414 u32 iop_tcnt;
415 u32 rsvd;
416 u32 phy_state[8];
417 u32 gpio_input_val;
418 u32 rsvd1[2];
419 u32 recover_err_info[8];
422 u32 gst_len_mpistate;
423 u32 iq_freeze_state0;
424 u32 iq_freeze_state1;
425 u32 msgu_tcnt;
426 u32 iop_tcnt;
427 u32 rsvd[9];
428 u32 gpio_input_val;
429 u32 rsvd1[2];
430 u32 recover_err_info[8];
434 u32 element_pri_size_cnt;
435 u32 upper_base_addr;
436 u32 lower_base_addr;
437 u32 ci_upper_base_addr;
438 u32 ci_lower_base_addr;
439 u32 pi_pci_bar;
440 u32 pi_offset;
441 u32 total_length;
444 u32 reserved;
446 u32 producer_idx;
449 u32 element_size_cnt;
450 u32 upper_base_addr;
451 u32 lower_base_addr;
453 u32 pi_upper_base_addr;
454 u32 pi_lower_base_addr;
455 u32 ci_pci_bar;
456 u32 ci_offset;
457 u32 total_length;
459 u32 interrup_vec_cnt_delay;
460 u32 dinterrup_to_pci_offset;
462 u32 consumer_idx;
467 u32 memsize;
471 u32 irq_id;
485 u32 fatal_bar_loc;
486 u32 forensic_last_offset;
487 u32 fatal_forensic_shift_offset;
488 u32 forensic_fatal_step;
489 u32 evtlog_ib_offset;
490 u32 evtlog_ob_offset;
509 u32 chip_id;
516 u32 id;
517 u32 irq;
518 u32 iomb_size; /* SPC and SPCV IOMB size */
529 u32 logging_level;
530 u32 fw_status;
531 u32 smp_exp_mode;
576 u32 cur_image_offset;
577 u32 cur_image_len;
578 u32 total_image_len;
583 u32 retcode;/*ret code (status)*/
584 u32 phase;/*ret code phase*/
585 u32 phaseCmplt;/*percent complete for the current
587 u32 version;/*Hex encoded firmware version number*/
588 u32 offset;/*Used for downloading firmware */
589 u32 len; /*len of buffer*/
590 u32 size;/* Used in OS VPD and Trace get size
592 u32 reserved;/* padding required for 64 bit
604 u32 len; /* len of buffer */
617 int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
619 u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
621 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
642 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
643 u32 mem_size, u32 align);
648 u32 opCode, void *payload, u32 responseQueue);
651 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
653 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
657 struct pm8001_device *pm8001_dev, u32 state);
661 void *fw_flash_updata_info, u32 tag);
669 u8 flag, u32 task_tag, u32 cmd_tag);
670 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
695 void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
697 u32 device_id);
700 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
702 u32 length, u8 *buf);
703 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
706 ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
713 u32 ccb_idx) in pm8001_ccb_task_free_done()