Lines Matching defs:mvumi_hw_regs
50 struct mvumi_hw_regs { struct
52 void *main_int_cause_reg;
53 void *enpointa_mask_reg;
54 void *enpointb_mask_reg;
55 void *rstoutn_en_reg;
56 void *ctrl_sts_reg;
57 void *rstoutn_mask_reg;
58 void *sys_soft_rst_reg;
61 void *pciea_to_arm_drbl_reg;
62 void *arm_to_pciea_drbl_reg;
63 void *arm_to_pciea_mask_reg;
64 void *pciea_to_arm_msg0;
65 void *pciea_to_arm_msg1;
66 void *arm_to_pciea_msg0;
67 void *arm_to_pciea_msg1;
70 void *reset_request;
71 void *reset_enable;
74 void *inb_list_basel;
75 void *inb_list_baseh;
76 void *inb_aval_count_basel;
77 void *inb_aval_count_baseh;
78 void *inb_write_pointer;
79 void *inb_read_pointer;
80 void *outb_list_basel;
81 void *outb_list_baseh;
82 void *outb_copy_basel;
83 void *outb_copy_baseh;
84 void *outb_copy_pointer;
85 void *outb_read_pointer;
86 void *inb_isr_cause;
87 void *outb_isr_cause;
88 void *outb_coal_cfg;
89 void *outb_coal_timeout;
92 u32 int_comaout;
93 u32 int_comaerr;
94 u32 int_dl_cpu2pciea;
95 u32 int_mu;
96 u32 int_drbl_int_mask;
97 u32 int_main_int_mask;
98 u32 cl_pointer_toggle;
99 u32 cl_slot_num_mask;
100 u32 clic_irq;
101 u32 clic_in_err;
102 u32 clic_out_err;