128 	void __iomem *vaddr;  member
359 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command()
360 	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);  in SA5_submit_command()
366 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command_no_read()
372 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command_ioaccel2()
384 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
385 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
389 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
390 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
398 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
399 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
403 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
404 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
418 		(void) readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
419 		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);  in SA5_performant_completed()
423 		(void) readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
449 		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);  in SA5_completed()
470 		readl(h->vaddr + SA5_INTR_STATUS);  in SA5_intr_pending()
476 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_performant_intr_pending()
482 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_intr_pending()
490 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_ioaccel_mode1_intr_pending()
520 		writel((q << 24) | rq->current_entry, h->vaddr +  in SA5_ioaccel_mode1_completed()