32 	void (*submit_command)(struct ctlr_info *h,
34 	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 	bool (*intr_pending)(struct ctlr_info *h);
36 	unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
356 static void SA5_submit_command(struct ctlr_info *h,  in SA5_submit_command()  argument
359 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command()
360 	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);  in SA5_submit_command()
363 static void SA5_submit_command_no_read(struct ctlr_info *h,  in SA5_submit_command_no_read()  argument
366 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command_no_read()
369 static void SA5_submit_command_ioaccel2(struct ctlr_info *h,  in SA5_submit_command_ioaccel2()  argument
372 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command_ioaccel2()
380 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)  in SA5_intr_mask()  argument
383 		h->interrupts_enabled = 1;  in SA5_intr_mask()
384 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
385 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
387 		h->interrupts_enabled = 0;  in SA5_intr_mask()
389 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
390 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
394 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)  in SA5_performant_intr_mask()  argument
397 		h->interrupts_enabled = 1;  in SA5_performant_intr_mask()
398 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
399 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
401 		h->interrupts_enabled = 0;  in SA5_performant_intr_mask()
403 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
404 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
408 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)  in SA5_performant_completed()  argument
410 	struct reply_queue_buffer *rq = &h->reply_queue[q];  in SA5_performant_completed()
414 	if (unlikely(!(h->msi_vector || h->msix_vector))) {  in SA5_performant_completed()
418 		(void) readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
419 		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);  in SA5_performant_completed()
423 		(void) readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
429 		atomic_dec(&h->commands_outstanding);  in SA5_performant_completed()
434 	if (rq->current_entry == h->max_commands) {  in SA5_performant_completed()
445 static unsigned long SA5_completed(struct ctlr_info *h,  in SA5_completed()  argument
449 		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);  in SA5_completed()
452 		atomic_dec(&h->commands_outstanding);  in SA5_completed()
456 		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",  in SA5_completed()
459 		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");  in SA5_completed()
467 static bool SA5_intr_pending(struct ctlr_info *h)  in SA5_intr_pending()  argument
470 		readl(h->vaddr + SA5_INTR_STATUS);  in SA5_intr_pending()
474 static bool SA5_performant_intr_pending(struct ctlr_info *h)  in SA5_performant_intr_pending()  argument
476 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_performant_intr_pending()
482 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_intr_pending()
488 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)  in SA5_ioaccel_mode1_intr_pending()  argument
490 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_ioaccel_mode1_intr_pending()
501 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)  in SA5_ioaccel_mode1_completed()  argument
504 	struct reply_queue_buffer *rq = &h->reply_queue[q];  in SA5_ioaccel_mode1_completed()
506 	BUG_ON(q >= h->nreply_queues);  in SA5_ioaccel_mode1_completed()
520 		writel((q << 24) | rq->current_entry, h->vaddr +  in SA5_ioaccel_mode1_completed()
522 		atomic_dec(&h->commands_outstanding);  in SA5_ioaccel_mode1_completed()