770     writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */  in gdth_init_isa()
780     writeb(0xff, &dp2_ptr->io.irqdel);  in gdth_init_isa()
781     writeb(0x00, &dp2_ptr->io.irqen);  in gdth_init_isa()
782     writeb(0x00, &dp2_ptr->u.ic.S_Status);  in gdth_init_isa()
783     writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);  in gdth_init_isa()
803     writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);  in gdth_init_isa()
804     writeb(0, &dp2_ptr->io.event);  in gdth_init_isa()
816     writeb(0, &dp2_ptr->u.ic.Status);  in gdth_init_isa()
817     writeb(0xff, &dp2_ptr->io.irqdel);  in gdth_init_isa()
835     writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);  in gdth_init_isa()
836     writeb(0, &dp2_ptr->io.event);  in gdth_init_isa()
847     writeb(0, &dp2_ptr->u.ic.Status);  in gdth_init_isa()
848     writeb(0xff, &dp2_ptr->io.irqdel);  in gdth_init_isa()
932         writeb(0xff, &dp6_ptr->io.irqdel);  in gdth_init_pci()
933         writeb(0x00, &dp6_ptr->io.irqen);  in gdth_init_pci()
934         writeb(0x00, &dp6_ptr->u.ic.S_Status);  in gdth_init_pci()
935         writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);  in gdth_init_pci()
938         writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);  in gdth_init_pci()
939         writeb(0, &dp6_ptr->io.event);  in gdth_init_pci()
951         writeb(0, &dp6_ptr->u.ic.S_Status);  in gdth_init_pci()
952         writeb(0xff, &dp6_ptr->io.irqdel);  in gdth_init_pci()
967         writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);  in gdth_init_pci()
968         writeb(0, &dp6_ptr->io.event);  in gdth_init_pci()
979         writeb(0, &dp6_ptr->u.ic.S_Status);  in gdth_init_pci()
980         writeb(0xff, &dp6_ptr->io.irqdel);  in gdth_init_pci()
1044         writeb(0x00, &dp6c_ptr->u.ic.S_Status);  in gdth_init_pci()
1045         writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);  in gdth_init_pci()
1048         writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);  in gdth_init_pci()
1063         writeb(0, &dp6c_ptr->u.ic.Status);  in gdth_init_pci()
1078         writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);  in gdth_init_pci()
1092         writeb(0, &dp6c_ptr->u.ic.S_Status);  in gdth_init_pci()
1158         writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,  in gdth_init_pci()
1160         writeb(0xff, &dp6m_ptr->i960r.edoor_reg);  in gdth_init_pci()
1161         writeb(0x00, &dp6m_ptr->u.ic.S_Status);  in gdth_init_pci()
1162         writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);  in gdth_init_pci()
1165         writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);  in gdth_init_pci()
1166         writeb(1, &dp6m_ptr->i960r.ldoor_reg);  in gdth_init_pci()
1178         writeb(0, &dp6m_ptr->u.ic.S_Status);  in gdth_init_pci()
1193         writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);  in gdth_init_pci()
1194         writeb(1, &dp6m_ptr->i960r.ldoor_reg);  in gdth_init_pci()
1205         writeb(0, &dp6m_ptr->u.ic.S_Status);  in gdth_init_pci()
1208         writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);  in gdth_init_pci()
1209         writeb(1, &dp6m_ptr->i960r.ldoor_reg);  in gdth_init_pci()
1221         writeb(0, &dp6m_ptr->u.ic.S_Status);  in gdth_init_pci()
1250         writeb(1, &dp2_ptr->io.irqdel);  in gdth_enable_int()
1251         writeb(0, &dp2_ptr->u.ic.Cmd_Index);  in gdth_enable_int()
1252         writeb(1, &dp2_ptr->io.irqen);  in gdth_enable_int()
1255         writeb(1, &dp6_ptr->io.irqdel);  in gdth_enable_int()
1256         writeb(0, &dp6_ptr->u.ic.Cmd_Index);  in gdth_enable_int()
1257         writeb(1, &dp6_ptr->io.irqen);  in gdth_enable_int()
1263         writeb(0xff, &dp6m_ptr->i960r.edoor_reg);  in gdth_enable_int()
1264         writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,  in gdth_enable_int()
1341         writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);  in gdth_set_sema0()
1343         writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);  in gdth_set_sema0()
1347         writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);  in gdth_set_sema0()
1437         writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);  in gdth_release_event()
1439         writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);  in gdth_release_event()
1443         writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);  in gdth_release_event()
3044             writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */  in __gdth_interrupt()
3045             writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */  in __gdth_interrupt()
3046             writeb(0, &dp2_ptr->io.Sema1);     /* reset status semaphore */  in __gdth_interrupt()
3059             writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */  in __gdth_interrupt()
3060             writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */  in __gdth_interrupt()
3061             writeb(0, &dp6_ptr->io.Sema1);     /* reset status semaphore */  in __gdth_interrupt()
3121                 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);  in __gdth_interrupt()
3122                 writeb(0, &dp6m_ptr->i960r.sema1_reg);  in __gdth_interrupt()
3206         writeb(0xff, &dp6m_ptr->i960r.edoor_reg);  in __gdth_interrupt()
3207         writeb(0, &dp6m_ptr->i960r.sema1_reg);  in __gdth_interrupt()