Lines Matching refs:NCR5380_write
245 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR); /* Enable int's */ in dtc_detect()
339 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE); in NCR5380_pread()
341 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ); in NCR5380_pread()
343 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ | CSR_INT_BASE); in NCR5380_pread()
344 NCR5380_write(DTC_BLK_CNT, len >> 7); /* Block count */ in NCR5380_pread()
361 NCR5380_write(MODE_REG, 0); /* Clear the operating mode */ in NCR5380_pread()
390 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE); in NCR5380_pwrite()
393 NCR5380_write(DTC_CONTROL_REG, 0); in NCR5380_pwrite()
395 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR); in NCR5380_pwrite()
396 NCR5380_write(DTC_BLK_CNT, len >> 7); /* Block count */ in NCR5380_pwrite()
416 NCR5380_write(MODE_REG, 0); /* Clear the operating mode */ in NCR5380_pwrite()