Lines Matching refs:uint32_t

158 	uint32_t	reserved6;
209 	uint32_t	eqid;
235 	uint32_t		len;		/* Buffer size */
245 	uint32_t		nsge;		/* Number of SG elements */
246 	uint32_t		tmo;		/* Driver timeout */
247 	uint32_t		datadir;	/* Data direction */
328 	uint32_t		size1;
330 	uint32_t		size2;
343 	uint32_t		totlen;		/* Total length */
350 typedef void (*iq_handler_t)(struct csio_hw *, void *, uint32_t,
380 	uint32_t	n_tot_reqs;		/* Total no. of Requests */
381 	uint32_t	n_tot_rsps;		/* Total no. of responses */
382 	uint32_t	n_qwrap;		/* Queue wraps */
383 	uint32_t	n_eq_wr_split;		/* Number of split EQ WRs */
384 	uint32_t	n_qentry;		/* Queue entry */
385 	uint32_t	n_qempty;		/* Queue empty */
386 	uint32_t	n_qfull;		/* Queue fulls */
387 	uint32_t	n_rsp_unknown;		/* Unknown response type */
388 	uint32_t	n_stray_comp;		/* Stray completion intr */
389 	uint32_t	n_flq_refill;		/* Number of FL refills */
398 	uint32_t		wr_sz;		/* Size of all WRs in this q
407 	uint32_t		credits;	/* Size of queue in credits */
418 	uint32_t		portid;		/* PCIE Channel */
419 	uint32_t		size;		/* Size of queue in bytes */
424 	uint32_t	csio_fl_align;		/* Calculated and cached
427 	uint32_t	sge_control;		/* padding, boundaries,
430 	uint32_t	sge_host_page_size;	/* Host page size */
431 	uint32_t	sge_fl_buf_size[CSIO_SGE_FL_SIZE_REGS];
444 	uint32_t		fw_iq_start;	/* Start ID of IQ for this fn*/
445 	uint32_t		fw_eq_start;	/* Start ID of EQ for this fn*/
483 int csio_wr_alloc_q(struct csio_hw *, uint32_t, uint32_t,
484 		    uint16_t, void *, uint32_t, int, iq_handler_t);
486 				uint32_t, uint8_t, bool,
493 int csio_wr_get(struct csio_hw *, int, uint32_t,
495 void csio_wr_copy_to_wrp(void *, struct csio_wr_pair *, uint32_t, uint32_t);
499 					  uint32_t, struct csio_fl_dma_buf *,
504 					  uint32_t, struct csio_fl_dma_buf *,