57 csio_get_flbuf_size(struct csio_hw *hw, struct csio_sge *sge, uint32_t reg)  in csio_get_flbuf_size()  argument
59 	sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0_A +  in csio_get_flbuf_size()
65 csio_wr_fl_bufsz(struct csio_sge *sge, struct csio_dma_buf *buf)  in csio_wr_fl_bufsz()  argument
67 	return sge->sge_fl_buf_size[buf->paddr & 0xF];  in csio_wr_fl_bufsz()
74 	return (hw->wrm.sge.sge_control & EGRSTATUSPAGESIZE_F) ?  128 : 64;  in csio_wr_qstat_pgsz()
117 	struct csio_sge *sge = &wrm->sge;  in csio_wr_fill_fl()  local
125 		buf->len = sge->sge_fl_buf_size[sreg];  in csio_wr_fill_fl()
1044 	struct csio_sge *sge = &wrm->sge;  in csio_wr_process_fl()  local
1070 		bufsz = csio_wr_fl_bufsz(sge, buf);  in csio_wr_process_fl()
1091 		flq->un.fl.offset += ALIGN(lastlen, sge->csio_fl_align);  in csio_wr_process_fl()
1307 	struct csio_sge *sge = &wrm->sge;  in csio_wr_fixup_host_params()  local
1319 	sge->csio_fl_align = clsz < 32 ? 32 : clsz;  in csio_wr_fixup_host_params()
1320 	ingpad = ilog2(sge->csio_fl_align) - 5;  in csio_wr_fixup_host_params()
1338 			sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),  in csio_wr_fixup_host_params()
1342 			sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),  in csio_wr_fixup_host_params()
1361 	struct csio_sge *sge = &wrm->sge;  in csio_init_intr_coalesce_parms()  local
1363 	csio_sge_thresh_reg = csio_closest_thresh(sge, csio_intr_coalesce_cnt);  in csio_init_intr_coalesce_parms()
1370 	csio_sge_timer_reg = csio_closest_timer(sge, csio_intr_coalesce_time);  in csio_init_intr_coalesce_parms()
1383 	struct csio_sge *sge = &wrm->sge;  in csio_wr_get_sge()  local
1389 	sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A);  in csio_wr_get_sge()
1391 	ingpad = INGPADBOUNDARY_G(sge->sge_control);  in csio_wr_get_sge()
1395 		sge->csio_fl_align = 32; break;  in csio_wr_get_sge()
1397 		sge->csio_fl_align = 64; break;  in csio_wr_get_sge()
1399 		sge->csio_fl_align = 128; break;  in csio_wr_get_sge()
1401 		sge->csio_fl_align = 256; break;  in csio_wr_get_sge()
1403 		sge->csio_fl_align = 512; break;  in csio_wr_get_sge()
1405 		sge->csio_fl_align = 1024; break;  in csio_wr_get_sge()
1407 		sge->csio_fl_align = 2048; break;  in csio_wr_get_sge()
1409 		sge->csio_fl_align = 4096; break;  in csio_wr_get_sge()
1413 		csio_get_flbuf_size(hw, sge, i);  in csio_wr_get_sge()
1419 	sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw,  in csio_wr_get_sge()
1421 	sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw,  in csio_wr_get_sge()
1423 	sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw,  in csio_wr_get_sge()
1425 	sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw,  in csio_wr_get_sge()
1427 	sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw,  in csio_wr_get_sge()
1429 	sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw,  in csio_wr_get_sge()
1433 	sge->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);  in csio_wr_get_sge()
1434 	sge->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold);  in csio_wr_get_sge()
1435 	sge->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold);  in csio_wr_get_sge()
1436 	sge->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold);  in csio_wr_get_sge()
1452 	struct csio_sge *sge = &wrm->sge;  in csio_wr_set_sge()  local
1461 	sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A);  in csio_wr_set_sge()
1482 	csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE2 + sge->csio_fl_align - 1)  in csio_wr_set_sge()
1483 		      & ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE2_A);  in csio_wr_set_sge()
1484 	csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE3 + sge->csio_fl_align - 1)  in csio_wr_set_sge()
1485 		      & ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE3_A);  in csio_wr_set_sge()
1493 		csio_get_flbuf_size(hw, sge, i);  in csio_wr_set_sge()
1496 	sge->timer_val[0] = CSIO_SGE_TIMER_VAL_0;  in csio_wr_set_sge()
1497 	sge->timer_val[1] = CSIO_SGE_TIMER_VAL_1;  in csio_wr_set_sge()
1498 	sge->timer_val[2] = CSIO_SGE_TIMER_VAL_2;  in csio_wr_set_sge()
1499 	sge->timer_val[3] = CSIO_SGE_TIMER_VAL_3;  in csio_wr_set_sge()
1500 	sge->timer_val[4] = CSIO_SGE_TIMER_VAL_4;  in csio_wr_set_sge()
1501 	sge->timer_val[5] = CSIO_SGE_TIMER_VAL_5;  in csio_wr_set_sge()
1503 	sge->counter_val[0] = CSIO_SGE_INT_CNT_VAL_0;  in csio_wr_set_sge()
1504 	sge->counter_val[1] = CSIO_SGE_INT_CNT_VAL_1;  in csio_wr_set_sge()
1505 	sge->counter_val[2] = CSIO_SGE_INT_CNT_VAL_2;  in csio_wr_set_sge()
1506 	sge->counter_val[3] = CSIO_SGE_INT_CNT_VAL_3;  in csio_wr_set_sge()
1508 	csio_wr_reg32(hw, THRESHOLD_0_V(sge->counter_val[0]) |  in csio_wr_set_sge()
1509 		      THRESHOLD_1_V(sge->counter_val[1]) |  in csio_wr_set_sge()
1510 		      THRESHOLD_2_V(sge->counter_val[2]) |  in csio_wr_set_sge()
1511 		      THRESHOLD_3_V(sge->counter_val[3]),  in csio_wr_set_sge()
1515 		   TIMERVALUE0_V(csio_us_to_core_ticks(hw, sge->timer_val[0])) |  in csio_wr_set_sge()
1516 		   TIMERVALUE1_V(csio_us_to_core_ticks(hw, sge->timer_val[1])),  in csio_wr_set_sge()
1520 		   TIMERVALUE2_V(csio_us_to_core_ticks(hw, sge->timer_val[2])) |  in csio_wr_set_sge()
1521 		   TIMERVALUE3_V(csio_us_to_core_ticks(hw, sge->timer_val[3])),  in csio_wr_set_sge()
1525 		   TIMERVALUE4_V(csio_us_to_core_ticks(hw, sge->timer_val[4])) |  in csio_wr_set_sge()
1526 		   TIMERVALUE5_V(csio_us_to_core_ticks(hw, sge->timer_val[5])),  in csio_wr_set_sge()