Lines Matching refs:u_int
578 u_int sg_count;/* How full ahc_dma_seg is */
733 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
734 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
927 u_int untagged_queue_lock;
1005 u_int num_critical_sections;
1038 u_int msgout_len; /* Length of message to send */
1039 u_int msgout_index; /* Current index in msgout */
1040 u_int msgin_index; /* Current index in msgin */
1059 u_int enabled_luns;
1062 u_int init_level;
1065 u_int pci_cachesize;
1072 u_int pci_target_perr_count;
1076 u_int instruction_ram_size;
1102 u_int target;
1103 u_int lun;
1150 u_int port);
1158 u_int tag, role_t role);
1184 char channel, int lun, u_int tag,
1193 char channel, int lun, u_int tag,
1201 u_int our_id, u_int target,
1202 u_int lun, char channel,
1205 const struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1206 u_int *ppr_options, u_int maxsync);
1207 u_int ahc_find_period(struct ahc_softc *ahc,
1208 u_int scsirate, u_int maxsync);
1225 u_int width, u_int type, int paused);
1229 u_int period, u_int offset,
1230 u_int ppr_options,
1231 u_int type, int paused);
1274 u_int num_entries,
1276 u_int address,
1277 u_int value,
1278 u_int *cur_column,
1279 u_int wrap_point);