Lines Matching refs:ACT88xx_REG
176 #define ACT88xx_REG(_name, _family, _id, _vsel_reg, _supply) \ macro
194 ACT88xx_REG("DCDC1", ACT8600, DCDC1, VSET, "vp1"),
195 ACT88xx_REG("DCDC2", ACT8600, DCDC2, VSET, "vp2"),
196 ACT88xx_REG("DCDC3", ACT8600, DCDC3, VSET, "vp3"),
211 ACT88xx_REG("LDO5", ACT8600, LDO5, VSET, "inl"),
212 ACT88xx_REG("LDO6", ACT8600, LDO6, VSET, "inl"),
213 ACT88xx_REG("LDO7", ACT8600, LDO7, VSET, "inl"),
214 ACT88xx_REG("LDO8", ACT8600, LDO8, VSET, "inl"),
240 ACT88xx_REG("REG1", ACT8846, REG1, VSET, "vp1"),
241 ACT88xx_REG("REG2", ACT8846, REG2, VSET0, "vp2"),
242 ACT88xx_REG("REG3", ACT8846, REG3, VSET0, "vp3"),
243 ACT88xx_REG("REG4", ACT8846, REG4, VSET0, "vp4"),
244 ACT88xx_REG("REG5", ACT8846, REG5, VSET, "inl1"),
245 ACT88xx_REG("REG6", ACT8846, REG6, VSET, "inl1"),
246 ACT88xx_REG("REG7", ACT8846, REG7, VSET, "inl1"),
247 ACT88xx_REG("REG8", ACT8846, REG8, VSET, "inl2"),
248 ACT88xx_REG("REG9", ACT8846, REG9, VSET, "inl2"),
249 ACT88xx_REG("REG10", ACT8846, REG10, VSET, "inl3"),
250 ACT88xx_REG("REG11", ACT8846, REG11, VSET, "inl3"),
251 ACT88xx_REG("REG12", ACT8846, REG12, VSET, "inl3"),
255 ACT88xx_REG("DCDC_REG1", ACT8865, DCDC1, VSET1, "vp1"),
256 ACT88xx_REG("DCDC_REG2", ACT8865, DCDC2, VSET1, "vp2"),
257 ACT88xx_REG("DCDC_REG3", ACT8865, DCDC3, VSET1, "vp3"),
258 ACT88xx_REG("LDO_REG1", ACT8865, LDO1, VSET, "inl45"),
259 ACT88xx_REG("LDO_REG2", ACT8865, LDO2, VSET, "inl45"),
260 ACT88xx_REG("LDO_REG3", ACT8865, LDO3, VSET, "inl67"),
261 ACT88xx_REG("LDO_REG4", ACT8865, LDO4, VSET, "inl67"),