41 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch);
42 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch);
504 		int ch;  in tsi721_irqhandler()  local
519 			for (ch = 4; ch < RIO_MAX_MBOX + 4; ch++) {  in tsi721_irqhandler()
520 				if (!(dev_ch_int & TSI721_INT_IMSG_CHAN(ch)))  in tsi721_irqhandler()
522 				tsi721_imsg_handler(priv, ch);  in tsi721_irqhandler()
536 			for (ch = 0; ch < RIO_MAX_MBOX; ch++) {  in tsi721_irqhandler()
537 				if (!(dev_ch_int & TSI721_INT_OMSG_CHAN(ch)))  in tsi721_irqhandler()
539 				tsi721_omsg_handler(priv, ch);  in tsi721_irqhandler()
553 		int ch;  in tsi721_irqhandler()  local
559 			for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) {  in tsi721_irqhandler()
560 				if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch)))  in tsi721_irqhandler()
562 				tsi721_bdma_handler(&priv->bdma[ch]);  in tsi721_irqhandler()
1172 tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch,  in tsi721_imsg_interrupt_enable()  argument
1181 	iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));  in tsi721_imsg_interrupt_enable()
1184 	rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_imsg_interrupt_enable()
1185 	iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_imsg_interrupt_enable()
1196 	iowrite32(rval | TSI721_INT_IMSG_CHAN(ch),  in tsi721_imsg_interrupt_enable()
1202 tsi721_imsg_interrupt_disable(struct tsi721_device *priv, int ch,  in tsi721_imsg_interrupt_disable()  argument
1211 	iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));  in tsi721_imsg_interrupt_disable()
1214 	rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_imsg_interrupt_disable()
1216 	iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_imsg_interrupt_disable()
1227 	rval &= ~TSI721_INT_IMSG_CHAN(ch);  in tsi721_imsg_interrupt_disable()
1233 tsi721_omsg_interrupt_enable(struct tsi721_device *priv, int ch,  in tsi721_omsg_interrupt_enable()  argument
1242 	iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));  in tsi721_omsg_interrupt_enable()
1245 	rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_omsg_interrupt_enable()
1246 	iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_omsg_interrupt_enable()
1257 	iowrite32(rval | TSI721_INT_OMSG_CHAN(ch),  in tsi721_omsg_interrupt_enable()
1263 tsi721_omsg_interrupt_disable(struct tsi721_device *priv, int ch,  in tsi721_omsg_interrupt_disable()  argument
1272 	iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));  in tsi721_omsg_interrupt_disable()
1275 	rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_omsg_interrupt_disable()
1277 	iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_omsg_interrupt_disable()
1288 	rval &= ~TSI721_INT_OMSG_CHAN(ch);  in tsi721_omsg_interrupt_disable()
1361 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch)  in tsi721_omsg_handler()  argument
1365 	spin_lock(&priv->omsg_ring[ch].lock);  in tsi721_omsg_handler()
1367 	omsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch));  in tsi721_omsg_handler()
1371 			"OB MBOX%d: Status FIFO is full\n", ch);  in tsi721_omsg_handler()
1384 		srd_ptr = priv->omsg_ring[ch].sts_rdptr;  in tsi721_omsg_handler()
1385 		sts_ptr = priv->omsg_ring[ch].sts_base;  in tsi721_omsg_handler()
1395 			srd_ptr %= priv->omsg_ring[ch].sts_size;  in tsi721_omsg_handler()
1402 		priv->omsg_ring[ch].sts_rdptr = srd_ptr;  in tsi721_omsg_handler()
1403 		iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch));  in tsi721_omsg_handler()
1405 		if (!priv->mport->outb_msg[ch].mcback)  in tsi721_omsg_handler()
1410 		tx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/  in tsi721_omsg_handler()
1418 		if (tx_slot == priv->omsg_ring[ch].size) {  in tsi721_omsg_handler()
1421 					(u64)priv->omsg_ring[ch].omd_phys)/  in tsi721_omsg_handler()
1429 		if (tx_slot == priv->omsg_ring[ch].size)  in tsi721_omsg_handler()
1431 		BUG_ON(tx_slot >= priv->omsg_ring[ch].size);  in tsi721_omsg_handler()
1432 		priv->mport->outb_msg[ch].mcback(priv->mport,  in tsi721_omsg_handler()
1433 				priv->omsg_ring[ch].dev_id, ch,  in tsi721_omsg_handler()
1446 			ioread32(priv->regs + TSI721_OBDMAC_STS(ch)));  in tsi721_omsg_handler()
1449 				priv->regs + TSI721_OBDMAC_INT(ch));  in tsi721_omsg_handler()
1451 				priv->regs + TSI721_OBDMAC_CTL(ch));  in tsi721_omsg_handler()
1452 		ioread32(priv->regs + TSI721_OBDMAC_CTL(ch));  in tsi721_omsg_handler()
1455 		if (priv->mport->outb_msg[ch].mcback)  in tsi721_omsg_handler()
1456 			priv->mport->outb_msg[ch].mcback(priv->mport,  in tsi721_omsg_handler()
1457 					priv->omsg_ring[ch].dev_id, ch,  in tsi721_omsg_handler()
1458 					priv->omsg_ring[ch].tx_slot);  in tsi721_omsg_handler()
1460 		iowrite32(priv->omsg_ring[ch].tx_slot,  in tsi721_omsg_handler()
1461 			priv->regs + TSI721_OBDMAC_DRDCNT(ch));  in tsi721_omsg_handler()
1462 		ioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch));  in tsi721_omsg_handler()
1463 		priv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot;  in tsi721_omsg_handler()
1464 		priv->omsg_ring[ch].sts_rdptr = 0;  in tsi721_omsg_handler()
1468 	iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch));  in tsi721_omsg_handler()
1475 		ch_inte |= TSI721_INT_OMSG_CHAN(ch);  in tsi721_omsg_handler()
1479 	spin_unlock(&priv->omsg_ring[ch].lock);  in tsi721_omsg_handler()
1730 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch)  in tsi721_imsg_handler()  argument
1732 	u32 mbox = ch - 4;  in tsi721_imsg_handler()
1737 	imsg_int = ioread32(priv->regs + TSI721_IBDMAC_INT(ch));  in tsi721_imsg_handler()
1752 	iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch));  in tsi721_imsg_handler()
1765 		ch_inte |= TSI721_INT_IMSG_CHAN(ch);  in tsi721_imsg_handler()
1783 	int ch = mbox + 4;  in tsi721_open_inb_mbox()  local
1873 		priv->regs + TSI721_IBDMAC_FQBH(ch));  in tsi721_open_inb_mbox()
1876 		priv->regs+TSI721_IBDMAC_FQBL(ch));  in tsi721_open_inb_mbox()
1878 		priv->regs + TSI721_IBDMAC_FQSZ(ch));  in tsi721_open_inb_mbox()
1882 		priv->regs + TSI721_IBDMAC_DQBH(ch));  in tsi721_open_inb_mbox()
1885 		priv->regs+TSI721_IBDMAC_DQBL(ch));  in tsi721_open_inb_mbox()
1887 		priv->regs + TSI721_IBDMAC_DQSZ(ch));  in tsi721_open_inb_mbox()
1923 	tsi721_imsg_interrupt_enable(priv, ch, TSI721_IBDMAC_INT_ALL);  in tsi721_open_inb_mbox()
1926 	iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch));  in tsi721_open_inb_mbox()
1927 	ioread32(priv->regs + TSI721_IBDMAC_CTL(ch));  in tsi721_open_inb_mbox()
1930 	iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch));  in tsi721_open_inb_mbox()
1974 	int ch = mbox + 4;  in tsi721_close_inb_mbox()  local
1983 	tsi721_imsg_interrupt_disable(priv, ch, TSI721_OBDMAC_INT_MASK);  in tsi721_close_inb_mbox()
2069 	int ch = mbox + 4;  in tsi721_get_inb_message()  local
2106 		priv->regs + TSI721_IBDMAC_DQRP(ch));  in tsi721_get_inb_message()
2116 		priv->regs + TSI721_IBDMAC_FQWP(ch));  in tsi721_get_inb_message()
2129 	int	ch;  in tsi721_messages_init()  local
2139 	for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) {  in tsi721_messages_init()
2142 			priv->regs + TSI721_IBDMAC_INT(ch));  in tsi721_messages_init()
2144 		iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch));  in tsi721_messages_init()
2147 				priv->regs + TSI721_SMSG_ECC_COR_LOG(ch));  in tsi721_messages_init()
2149 				priv->regs + TSI721_SMSG_ECC_NCOR(ch));  in tsi721_messages_init()
2161 	int ch;  in tsi721_disable_ints()  local
2170 	for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++)  in tsi721_disable_ints()
2171 		iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch));  in tsi721_disable_ints()
2174 	for (ch = 0; ch < TSI721_OMSG_CHNUM; ch++)  in tsi721_disable_ints()
2175 		iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch));  in tsi721_disable_ints()
2181 	for (ch = 0; ch < TSI721_DMA_MAXCH; ch++)  in tsi721_disable_ints()
2183 			priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE);  in tsi721_disable_ints()
2189 	for (ch = 0; ch < TSI721_SRIO_MAXCH; ch++)  in tsi721_disable_ints()
2190 		iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch));  in tsi721_disable_ints()