52 	void __iomem	*mmio_base;  member
93 	reg_val = readw(pc->mmio_base + ECCTL2);  in ecap_pwm_config()
98 	writew(reg_val, pc->mmio_base + ECCTL2);  in ecap_pwm_config()
102 		writel(duty_cycles, pc->mmio_base + CAP2);  in ecap_pwm_config()
103 		writel(period_cycles, pc->mmio_base + CAP1);  in ecap_pwm_config()
110 		writel(duty_cycles, pc->mmio_base + CAP4);  in ecap_pwm_config()
111 		writel(period_cycles, pc->mmio_base + CAP3);  in ecap_pwm_config()
115 		reg_val = readw(pc->mmio_base + ECCTL2);  in ecap_pwm_config()
118 		writew(reg_val, pc->mmio_base + ECCTL2);  in ecap_pwm_config()
132 	reg_val = readw(pc->mmio_base + ECCTL2);  in ecap_pwm_set_polarity()
140 	writew(reg_val, pc->mmio_base + ECCTL2);  in ecap_pwm_set_polarity()
157 	reg_val = readw(pc->mmio_base + ECCTL2);  in ecap_pwm_enable()
159 	writew(reg_val, pc->mmio_base + ECCTL2);  in ecap_pwm_enable()
172 	reg_val = readw(pc->mmio_base + ECCTL2);  in ecap_pwm_disable()
174 	writew(reg_val, pc->mmio_base + ECCTL2);  in ecap_pwm_disable()
235 	pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);  in ecap_pwm_probe()
236 	if (IS_ERR(pc->mmio_base))  in ecap_pwm_probe()
237 		return PTR_ERR(pc->mmio_base);  in ecap_pwm_probe()
288 	pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);  in ecap_pwm_save_context()
289 	pc->ctx.cap4 = readl(pc->mmio_base + CAP4);  in ecap_pwm_save_context()
290 	pc->ctx.cap3 = readl(pc->mmio_base + CAP3);  in ecap_pwm_save_context()
296 	writel(pc->ctx.cap3, pc->mmio_base + CAP3);  in ecap_pwm_restore_context()
297 	writel(pc->ctx.cap4, pc->mmio_base + CAP4);  in ecap_pwm_restore_context()
298 	writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);  in ecap_pwm_restore_context()