308 static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)  in s3c64xx_gpio_irq_set_mask()  argument
310 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_set_mask()
312 	unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_set_mask()
324 static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)  in s3c64xx_gpio_irq_unmask()  argument
326 	s3c64xx_gpio_irq_set_mask(irqd, false);  in s3c64xx_gpio_irq_unmask()
329 static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)  in s3c64xx_gpio_irq_mask()  argument
331 	s3c64xx_gpio_irq_set_mask(irqd, true);  in s3c64xx_gpio_irq_mask()
334 static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)  in s3c64xx_gpio_irq_ack()  argument
336 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_ack()
338 	unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_ack()
344 static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)  in s3c64xx_gpio_irq_set_type()  argument
346 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_set_type()
359 	s3c64xx_irq_set_handler(irqd->irq, type);  in s3c64xx_gpio_irq_set_type()
363 	shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_set_type()
371 	s3c64xx_irq_set_function(d, bank, irqd->hwirq);  in s3c64xx_gpio_irq_set_type()
519 static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)  in s3c64xx_eint0_irq_set_mask()  argument
522 					irq_data_get_irq_chip_data(irqd);  in s3c64xx_eint0_irq_set_mask()
528 		val |= 1 << ddata->eints[irqd->hwirq];  in s3c64xx_eint0_irq_set_mask()
530 		val &= ~(1 << ddata->eints[irqd->hwirq]);  in s3c64xx_eint0_irq_set_mask()
534 static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)  in s3c64xx_eint0_irq_unmask()  argument
536 	s3c64xx_eint0_irq_set_mask(irqd, false);  in s3c64xx_eint0_irq_unmask()
539 static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)  in s3c64xx_eint0_irq_mask()  argument
541 	s3c64xx_eint0_irq_set_mask(irqd, true);  in s3c64xx_eint0_irq_mask()
544 static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)  in s3c64xx_eint0_irq_ack()  argument
547 					irq_data_get_irq_chip_data(irqd);  in s3c64xx_eint0_irq_ack()
550 	writel(1 << ddata->eints[irqd->hwirq],  in s3c64xx_eint0_irq_ack()
554 static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)  in s3c64xx_eint0_irq_set_type()  argument
557 					irq_data_get_irq_chip_data(irqd);  in s3c64xx_eint0_irq_set_type()
571 	s3c64xx_irq_set_handler(irqd->irq, type);  in s3c64xx_eint0_irq_set_type()
575 	shift = ddata->eints[irqd->hwirq];  in s3c64xx_eint0_irq_set_type()
587 	s3c64xx_irq_set_function(d, bank, irqd->hwirq);  in s3c64xx_eint0_irq_set_type()