Lines Matching refs:g
143 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
148 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
150 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
151 if (g->funcs[i] == function) in msm_pinmux_set_mux()
155 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
160 val = readl(pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
161 val &= ~(0x7 << g->mux_bit); in msm_pinmux_set_mux()
162 val |= i << g->mux_bit; in msm_pinmux_set_mux()
163 writel(val, pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
178 const struct msm_pingroup *g, in msm_config_reg() argument
188 *bit = g->pull_bit; in msm_config_reg()
192 *bit = g->drv_bit; in msm_config_reg()
197 *bit = g->oe_bit; in msm_config_reg()
221 const struct msm_pingroup *g; in msm_config_group_get() local
230 g = &pctrl->soc->groups[group]; in msm_config_group_get()
232 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
236 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_get()
261 val = readl(pctrl->regs + g->io_reg); in msm_config_group_get()
262 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
284 const struct msm_pingroup *g; in msm_config_group_set() local
295 g = &pctrl->soc->groups[group]; in msm_config_group_set()
301 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
329 val = readl(pctrl->regs + g->io_reg); in msm_config_group_set()
331 val |= BIT(g->out_bit); in msm_config_group_set()
333 val &= ~BIT(g->out_bit); in msm_config_group_set()
334 writel(val, pctrl->regs + g->io_reg); in msm_config_group_set()
357 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_set()
360 writel(val, pctrl->regs + g->ctl_reg); in msm_config_group_set()
382 const struct msm_pingroup *g; in msm_gpio_direction_input() local
387 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
391 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
392 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
393 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
402 const struct msm_pingroup *g; in msm_gpio_direction_output() local
407 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
411 val = readl(pctrl->regs + g->io_reg); in msm_gpio_direction_output()
413 val |= BIT(g->out_bit); in msm_gpio_direction_output()
415 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
416 writel(val, pctrl->regs + g->io_reg); in msm_gpio_direction_output()
418 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
419 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
420 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
429 const struct msm_pingroup *g; in msm_gpio_get() local
433 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
435 val = readl(pctrl->regs + g->io_reg); in msm_gpio_get()
436 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
441 const struct msm_pingroup *g; in msm_gpio_set() local
446 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
450 val = readl(pctrl->regs + g->io_reg); in msm_gpio_set()
452 val |= BIT(g->out_bit); in msm_gpio_set()
454 val &= ~BIT(g->out_bit); in msm_gpio_set()
455 writel(val, pctrl->regs + g->io_reg); in msm_gpio_set()
481 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
496 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
497 ctl_reg = readl(pctrl->regs + g->ctl_reg); in msm_gpio_dbg_show_one()
499 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
500 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
501 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
502 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
504 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); in msm_gpio_dbg_show_one()
555 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
563 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
565 pol = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_update_dual_edge_pos()
566 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
567 writel(pol, pctrl->regs + g->intr_cfg_reg); in msm_gpio_update_dual_edge_pos()
569 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
570 intstat = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_update_dual_edge_pos()
582 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
586 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
590 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_mask()
591 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
592 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_mask()
603 const struct msm_pingroup *g; in msm_gpio_irq_unmask() local
607 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
611 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_unmask()
612 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_unmask()
613 writel(val, pctrl->regs + g->intr_status_reg); in msm_gpio_irq_unmask()
615 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_unmask()
616 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
617 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_unmask()
628 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
632 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
636 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_ack()
637 if (g->intr_ack_high) in msm_gpio_irq_ack()
638 val |= BIT(g->intr_status_bit); in msm_gpio_irq_ack()
640 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_ack()
641 writel(val, pctrl->regs + g->intr_status_reg); in msm_gpio_irq_ack()
644 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
653 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
657 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
664 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
670 val = readl(pctrl->regs + g->intr_target_reg); in msm_gpio_irq_set_type()
671 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
672 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
673 writel(val, pctrl->regs + g->intr_target_reg); in msm_gpio_irq_set_type()
680 val = readl(pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_set_type()
681 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
682 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
683 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
684 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
687 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
688 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
691 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
692 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
695 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
696 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
701 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
704 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
705 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
706 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
709 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
710 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
713 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
716 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
717 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
722 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
728 writel(val, pctrl->regs + g->intr_cfg_reg); in msm_gpio_irq_set_type()
731 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
770 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
785 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
786 val = readl(pctrl->regs + g->intr_status_reg); in msm_gpio_irq_handler()
787 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()