153 	enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
154 	void (*mux_A_periph)(void __iomem *pio, unsigned mask);
155 	void (*mux_B_periph)(void __iomem *pio, unsigned mask);
156 	void (*mux_C_periph)(void __iomem *pio, unsigned mask);
157 	void (*mux_D_periph)(void __iomem *pio, unsigned mask);
159 	void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
161 	void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
163 	void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
165 	void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
363 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)  in at91_mux_disable_interrupt()  argument
365 	writel_relaxed(mask, pio + PIO_IDR);  in at91_mux_disable_interrupt()
373 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)  in at91_mux_set_pullup()  argument
376 		writel_relaxed(mask, pio + PIO_PPDDR);  in at91_mux_set_pullup()
378 	writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));  in at91_mux_set_pullup()
386 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)  in at91_mux_set_multidrive()  argument
388 	writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));  in at91_mux_set_multidrive()
391 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)  in at91_mux_set_A_periph()  argument
393 	writel_relaxed(mask, pio + PIO_ASR);  in at91_mux_set_A_periph()
396 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)  in at91_mux_set_B_periph()  argument
398 	writel_relaxed(mask, pio + PIO_BSR);  in at91_mux_set_B_periph()
401 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)  in at91_mux_pio3_set_A_periph()  argument
404 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,  in at91_mux_pio3_set_A_periph()
406 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,  in at91_mux_pio3_set_A_periph()
410 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)  in at91_mux_pio3_set_B_periph()  argument
412 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,  in at91_mux_pio3_set_B_periph()
414 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,  in at91_mux_pio3_set_B_periph()
418 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)  in at91_mux_pio3_set_C_periph()  argument
420 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);  in at91_mux_pio3_set_C_periph()
421 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);  in at91_mux_pio3_set_C_periph()
424 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)  in at91_mux_pio3_set_D_periph()  argument
426 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);  in at91_mux_pio3_set_D_periph()
427 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);  in at91_mux_pio3_set_D_periph()
430 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)  in at91_mux_pio3_get_periph()  argument
434 	if (readl_relaxed(pio + PIO_PSR) & mask)  in at91_mux_pio3_get_periph()
437 	select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);  in at91_mux_pio3_get_periph()
438 	select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);  in at91_mux_pio3_get_periph()
443 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)  in at91_mux_get_periph()  argument
447 	if (readl_relaxed(pio + PIO_PSR) & mask)  in at91_mux_get_periph()
450 	select = readl_relaxed(pio + PIO_ABSR) & mask;  in at91_mux_get_periph()
460 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)  in at91_mux_set_deglitch()  argument
462 	writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));  in at91_mux_set_deglitch()
473 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)  in at91_mux_pio3_set_deglitch()  argument
476 		writel_relaxed(mask, pio + PIO_IFSCDR);  in at91_mux_pio3_set_deglitch()
477 	at91_mux_set_deglitch(pio, mask, is_on);  in at91_mux_pio3_set_deglitch()
488 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,  in at91_mux_pio3_set_debounce()  argument
492 		writel_relaxed(mask, pio + PIO_IFSCER);  in at91_mux_pio3_set_debounce()
494 		writel_relaxed(mask, pio + PIO_IFER);  in at91_mux_pio3_set_debounce()
496 		writel_relaxed(mask, pio + PIO_IFSCDR);  in at91_mux_pio3_set_debounce()
504 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)  in at91_mux_pio3_set_pulldown()  argument
507 		writel_relaxed(mask, pio + PIO_PUDR);  in at91_mux_pio3_set_pulldown()
509 	writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));  in at91_mux_pio3_set_pulldown()
512 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)  in at91_mux_pio3_disable_schmitt_trig()  argument
514 	writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);  in at91_mux_pio3_disable_schmitt_trig()
697 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)  in at91_mux_gpio_disable()  argument
699 	writel_relaxed(mask, pio + PIO_PDR);  in at91_mux_gpio_disable()
702 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)  in at91_mux_gpio_enable()  argument
704 	writel_relaxed(mask, pio + PIO_PER);  in at91_mux_gpio_enable()
705 	writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));  in at91_mux_gpio_enable()
716 	unsigned mask;  in at91_pmx_set()  local
739 		mask = pin_to_mask(pin->pin);  in at91_pmx_set()
740 		at91_mux_disable_interrupt(pio, mask);  in at91_pmx_set()
743 			at91_mux_gpio_enable(pio, mask, 1);  in at91_pmx_set()
746 			info->ops->mux_A_periph(pio, mask);  in at91_pmx_set()
749 			info->ops->mux_B_periph(pio, mask);  in at91_pmx_set()
754 			info->ops->mux_C_periph(pio, mask);  in at91_pmx_set()
759 			info->ops->mux_D_periph(pio, mask);  in at91_pmx_set()
763 			at91_mux_gpio_disable(pio, mask);  in at91_pmx_set()
803 	unsigned mask;  in at91_gpio_request_enable()  local
818 	mask = 1 << (offset - chip->base);  in at91_gpio_request_enable()
821 		offset, 'A' + range->id, offset - chip->base, mask);  in at91_gpio_request_enable()
823 	writel_relaxed(mask, at91_chip->regbase + PIO_PER);  in at91_gpio_request_enable()
890 	unsigned mask;  in at91_pinconf_set()  local
908 		mask = pin_to_mask(pin);  in at91_pinconf_set()
913 		at91_mux_set_pullup(pio, mask, config & PULL_UP);  in at91_pinconf_set()
914 		at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);  in at91_pinconf_set()
916 			info->ops->set_deglitch(pio, mask, config & DEGLITCH);  in at91_pinconf_set()
918 			info->ops->set_debounce(pio, mask, config & DEBOUNCE,  in at91_pinconf_set()
921 			info->ops->set_pulldown(pio, mask, config & PULL_DOWN);  in at91_pinconf_set()
923 			info->ops->disable_schmitt_trig(pio, mask);  in at91_pinconf_set()
943 #define DBG_SHOW_FLAG_MASKED(mask,flag) do {	\  argument
944 	if ((config & mask) == flag) {		\
1306 	unsigned mask = 1 << offset;  in at91_gpio_get_direction()  local
1310 	return !(osr & mask);  in at91_gpio_get_direction()
1317 	unsigned mask = 1 << offset;  in at91_gpio_direction_input()  local
1319 	writel_relaxed(mask, pio + PIO_ODR);  in at91_gpio_direction_input()
1327 	unsigned mask = 1 << offset;  in at91_gpio_get()  local
1331 	return (pdsr & mask) != 0;  in at91_gpio_get()
1339 	unsigned mask = 1 << offset;  in at91_gpio_set()  local
1341 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));  in at91_gpio_set()
1349 	unsigned mask = 1 << offset;  in at91_gpio_direction_output()  local
1351 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));  in at91_gpio_direction_output()
1352 	writel_relaxed(mask, pio + PIO_OER);  in at91_gpio_direction_output()
1366 		unsigned mask = pin_to_mask(i);  in at91_gpio_dbg_show()  local
1372 		mode = at91_gpio->ops->get_periph(pio, mask);  in at91_gpio_dbg_show()
1378 				      readl_relaxed(pio + PIO_OSR) & mask ?  in at91_gpio_dbg_show()
1381 				      readl_relaxed(pio + PIO_PDSR) & mask ?  in at91_gpio_dbg_show()
1411 	unsigned	mask = 1 << d->hwirq;  in gpio_irq_mask()  local
1414 		writel_relaxed(mask, pio + PIO_IDR);  in gpio_irq_mask()
1421 	unsigned	mask = 1 << d->hwirq;  in gpio_irq_unmask()  local
1424 		writel_relaxed(mask, pio + PIO_IER);  in gpio_irq_unmask()
1443 	unsigned	mask = 1 << d->hwirq;  in alt_gpio_irq_type()  local
1448 		writel_relaxed(mask, pio + PIO_ESR);  in alt_gpio_irq_type()
1449 		writel_relaxed(mask, pio + PIO_REHLSR);  in alt_gpio_irq_type()
1453 		writel_relaxed(mask, pio + PIO_ESR);  in alt_gpio_irq_type()
1454 		writel_relaxed(mask, pio + PIO_FELLSR);  in alt_gpio_irq_type()
1458 		writel_relaxed(mask, pio + PIO_LSR);  in alt_gpio_irq_type()
1459 		writel_relaxed(mask, pio + PIO_FELLSR);  in alt_gpio_irq_type()
1463 		writel_relaxed(mask, pio + PIO_LSR);  in alt_gpio_irq_type()
1464 		writel_relaxed(mask, pio + PIO_REHLSR);  in alt_gpio_irq_type()
1472 		writel_relaxed(mask, pio + PIO_AIMDR);  in alt_gpio_irq_type()
1481 	writel_relaxed(mask, pio + PIO_AIMER);  in alt_gpio_irq_type()
1522 	unsigned mask = 1 << d->hwirq;  in gpio_irq_set_wake()  local
1528 		wakeups[bank] |= mask;  in gpio_irq_set_wake()
1530 		wakeups[bank] &= ~mask;  in gpio_irq_set_wake()