291 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_mode()  argument
297 	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;  in __nmk_gpio_set_mode()
298 	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;  in __nmk_gpio_set_mode()
303 	writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);  in __nmk_gpio_set_mode()
304 	writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);  in __nmk_gpio_set_mode()
307 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_slpm()  argument
313 	slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);  in __nmk_gpio_set_slpm()
318 	writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);  in __nmk_gpio_set_slpm()
321 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_pull()  argument
327 	pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);  in __nmk_gpio_set_pull()
330 		nmk_chip->pull_up &= ~bit;  in __nmk_gpio_set_pull()
335 	writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);  in __nmk_gpio_set_pull()
338 		nmk_chip->pull_up |= bit;  in __nmk_gpio_set_pull()
339 		writel(bit, nmk_chip->addr + NMK_GPIO_DATS);  in __nmk_gpio_set_pull()
341 		nmk_chip->pull_up &= ~bit;  in __nmk_gpio_set_pull()
342 		writel(bit, nmk_chip->addr + NMK_GPIO_DATC);  in __nmk_gpio_set_pull()
346 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_lowemi()  argument
350 	bool enabled = nmk_chip->lowemi & bit;  in __nmk_gpio_set_lowemi()
356 		nmk_chip->lowemi |= bit;  in __nmk_gpio_set_lowemi()
358 		nmk_chip->lowemi &= ~bit;  in __nmk_gpio_set_lowemi()
360 	writel_relaxed(nmk_chip->lowemi,  in __nmk_gpio_set_lowemi()
361 		       nmk_chip->addr + NMK_GPIO_LOWEMI);  in __nmk_gpio_set_lowemi()
364 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_make_input()  argument
367 	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);  in __nmk_gpio_make_input()
370 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_output()  argument
374 		writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);  in __nmk_gpio_set_output()
376 		writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);  in __nmk_gpio_set_output()
379 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_make_output()  argument
382 	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);  in __nmk_gpio_make_output()
383 	__nmk_gpio_set_output(nmk_chip, offset, val);  in __nmk_gpio_make_output()
386 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_mode_safe()  argument
390 	u32 rwimsc = nmk_chip->rwimsc;  in __nmk_gpio_set_mode_safe()
391 	u32 fwimsc = nmk_chip->fwimsc;  in __nmk_gpio_set_mode_safe()
393 	if (glitch && nmk_chip->set_ioforce) {  in __nmk_gpio_set_mode_safe()
397 		writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);  in __nmk_gpio_set_mode_safe()
398 		writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);  in __nmk_gpio_set_mode_safe()
400 		nmk_chip->set_ioforce(true);  in __nmk_gpio_set_mode_safe()
403 	__nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);  in __nmk_gpio_set_mode_safe()
405 	if (glitch && nmk_chip->set_ioforce) {  in __nmk_gpio_set_mode_safe()
406 		nmk_chip->set_ioforce(false);  in __nmk_gpio_set_mode_safe()
408 		writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);  in __nmk_gpio_set_mode_safe()
409 		writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);  in __nmk_gpio_set_mode_safe()
414 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)  in nmk_gpio_disable_lazy_irq()  argument
416 	u32 falling = nmk_chip->fimsc & BIT(offset);  in nmk_gpio_disable_lazy_irq()
417 	u32 rising = nmk_chip->rimsc & BIT(offset);  in nmk_gpio_disable_lazy_irq()
418 	int gpio = nmk_chip->chip.base + offset;  in nmk_gpio_disable_lazy_irq()
419 	int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);  in nmk_gpio_disable_lazy_irq()
429 		nmk_chip->rimsc &= ~BIT(offset);  in nmk_gpio_disable_lazy_irq()
430 		writel_relaxed(nmk_chip->rimsc,  in nmk_gpio_disable_lazy_irq()
431 			       nmk_chip->addr + NMK_GPIO_RIMSC);  in nmk_gpio_disable_lazy_irq()
435 		nmk_chip->fimsc &= ~BIT(offset);  in nmk_gpio_disable_lazy_irq()
436 		writel_relaxed(nmk_chip->fimsc,  in nmk_gpio_disable_lazy_irq()
437 			       nmk_chip->addr + NMK_GPIO_FIMSC);  in nmk_gpio_disable_lazy_irq()
440 	dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);  in nmk_gpio_disable_lazy_irq()
618 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_get_mode()  local
621 	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];  in nmk_gpio_get_mode()
622 	if (!nmk_chip)  in nmk_gpio_get_mode()
627 	clk_enable(nmk_chip->clk);  in nmk_gpio_get_mode()
629 	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;  in nmk_gpio_get_mode()
630 	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;  in nmk_gpio_get_mode()
632 	clk_disable(nmk_chip->clk);  in nmk_gpio_get_mode()
648 	struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);  in nmk_gpio_irq_ack()  local
650 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_ack()
651 	writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);  in nmk_gpio_irq_ack()
652 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_ack()
660 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_irq_modify()  argument
673 		rimscval = &nmk_chip->rimsc;  in __nmk_gpio_irq_modify()
674 		fimscval = &nmk_chip->fimsc;  in __nmk_gpio_irq_modify()
678 		rimscval = &nmk_chip->rwimsc;  in __nmk_gpio_irq_modify()
679 		fimscval = &nmk_chip->fwimsc;  in __nmk_gpio_irq_modify()
683 	if (nmk_chip->edge_rising & bitmask) {  in __nmk_gpio_irq_modify()
688 		writel(*rimscval, nmk_chip->addr + rimscreg);  in __nmk_gpio_irq_modify()
690 	if (nmk_chip->edge_falling & bitmask) {  in __nmk_gpio_irq_modify()
695 		writel(*fimscval, nmk_chip->addr + fimscreg);  in __nmk_gpio_irq_modify()
699 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_wake()  argument
707 	if (nmk_chip->sleepmode && on) {  in __nmk_gpio_set_wake()
708 		__nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,  in __nmk_gpio_set_wake()
712 	__nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);  in __nmk_gpio_set_wake()
717 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_irq_maskunmask()  local
721 	nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_maskunmask()
723 	if (!nmk_chip)  in nmk_gpio_irq_maskunmask()
726 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_maskunmask()
728 	spin_lock(&nmk_chip->lock);  in nmk_gpio_irq_maskunmask()
730 	__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);  in nmk_gpio_irq_maskunmask()
732 	if (!(nmk_chip->real_wake & bitmask))  in nmk_gpio_irq_maskunmask()
733 		__nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);  in nmk_gpio_irq_maskunmask()
735 	spin_unlock(&nmk_chip->lock);  in nmk_gpio_irq_maskunmask()
737 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_maskunmask()
754 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_irq_set_wake()  local
758 	nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_set_wake()
759 	if (!nmk_chip)  in nmk_gpio_irq_set_wake()
763 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_set_wake()
765 	spin_lock(&nmk_chip->lock);  in nmk_gpio_irq_set_wake()
768 		__nmk_gpio_set_wake(nmk_chip, d->hwirq, on);  in nmk_gpio_irq_set_wake()
771 		nmk_chip->real_wake |= bitmask;  in nmk_gpio_irq_set_wake()
773 		nmk_chip->real_wake &= ~bitmask;  in nmk_gpio_irq_set_wake()
775 	spin_unlock(&nmk_chip->lock);  in nmk_gpio_irq_set_wake()
777 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_set_wake()
786 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_irq_set_type()  local
790 	nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_set_type()
792 	if (!nmk_chip)  in nmk_gpio_irq_set_type()
799 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_set_type()
800 	spin_lock_irqsave(&nmk_chip->lock, flags);  in nmk_gpio_irq_set_type()
803 		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);  in nmk_gpio_irq_set_type()
806 		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);  in nmk_gpio_irq_set_type()
808 	nmk_chip->edge_rising &= ~bitmask;  in nmk_gpio_irq_set_type()
810 		nmk_chip->edge_rising |= bitmask;  in nmk_gpio_irq_set_type()
812 	nmk_chip->edge_falling &= ~bitmask;  in nmk_gpio_irq_set_type()
814 		nmk_chip->edge_falling |= bitmask;  in nmk_gpio_irq_set_type()
817 		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);  in nmk_gpio_irq_set_type()
820 		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);  in nmk_gpio_irq_set_type()
822 	spin_unlock_irqrestore(&nmk_chip->lock, flags);  in nmk_gpio_irq_set_type()
823 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_set_type()
830 	struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_startup()  local
832 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_startup()
839 	struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_shutdown()  local
842 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_shutdown()
878 	struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);  in nmk_gpio_irq_handler()  local
881 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_handler()
882 	status = readl(nmk_chip->addr + NMK_GPIO_IS);  in nmk_gpio_irq_handler()
883 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_handler()
892 	struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);  in nmk_gpio_latent_irq_handler()  local
893 	u32 status = nmk_chip->get_latent_status(nmk_chip->bank);  in nmk_gpio_latent_irq_handler()
920 	struct nmk_gpio_chip *nmk_chip =  in nmk_gpio_make_input()  local
923 	clk_enable(nmk_chip->clk);  in nmk_gpio_make_input()
925 	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);  in nmk_gpio_make_input()
927 	clk_disable(nmk_chip->clk);  in nmk_gpio_make_input()
934 	struct nmk_gpio_chip *nmk_chip =  in nmk_gpio_get_input()  local
939 	clk_enable(nmk_chip->clk);  in nmk_gpio_get_input()
941 	value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;  in nmk_gpio_get_input()
943 	clk_disable(nmk_chip->clk);  in nmk_gpio_get_input()
951 	struct nmk_gpio_chip *nmk_chip =  in nmk_gpio_set_output()  local
954 	clk_enable(nmk_chip->clk);  in nmk_gpio_set_output()
956 	__nmk_gpio_set_output(nmk_chip, offset, val);  in nmk_gpio_set_output()
958 	clk_disable(nmk_chip->clk);  in nmk_gpio_set_output()
964 	struct nmk_gpio_chip *nmk_chip =  in nmk_gpio_make_output()  local
967 	clk_enable(nmk_chip->clk);  in nmk_gpio_make_output()
969 	__nmk_gpio_make_output(nmk_chip, offset, val);  in nmk_gpio_make_output()
971 	clk_disable(nmk_chip->clk);  in nmk_gpio_make_output()
985 	struct nmk_gpio_chip *nmk_chip =  in nmk_gpio_dbg_show_one()  local
1008 	clk_enable(nmk_chip->clk);  in nmk_gpio_dbg_show_one()
1009 	is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);  in nmk_gpio_dbg_show_one()
1010 	pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);  in nmk_gpio_dbg_show_one()
1011 	data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit);  in nmk_gpio_dbg_show_one()
1043 			if (nmk_chip->edge_rising & bitmask)  in nmk_gpio_dbg_show_one()
1045 			else if (nmk_chip->edge_falling & bitmask)  in nmk_gpio_dbg_show_one()
1056 	clk_disable(nmk_chip->clk);  in nmk_gpio_dbg_show_one()
1191 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_probe()  local
1228 	nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);  in nmk_gpio_probe()
1229 	if (!nmk_chip)  in nmk_gpio_probe()
1236 	nmk_chip->bank = dev->id;  in nmk_gpio_probe()
1237 	nmk_chip->clk = clk;  in nmk_gpio_probe()
1238 	nmk_chip->addr = base;  in nmk_gpio_probe()
1239 	nmk_chip->chip = nmk_gpio_template;  in nmk_gpio_probe()
1240 	nmk_chip->parent_irq = irq;  in nmk_gpio_probe()
1241 	nmk_chip->latent_parent_irq = latent_irq;  in nmk_gpio_probe()
1242 	nmk_chip->sleepmode = supports_sleepmode;  in nmk_gpio_probe()
1243 	spin_lock_init(&nmk_chip->lock);  in nmk_gpio_probe()
1245 	chip = &nmk_chip->chip;  in nmk_gpio_probe()
1252 	clk_enable(nmk_chip->clk);  in nmk_gpio_probe()
1253 	nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);  in nmk_gpio_probe()
1254 	clk_disable(nmk_chip->clk);  in nmk_gpio_probe()
1257 	ret = gpiochip_add(&nmk_chip->chip);  in nmk_gpio_probe()
1261 	BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));  in nmk_gpio_probe()
1263 	nmk_gpio_chips[nmk_chip->bank] = nmk_chip;  in nmk_gpio_probe()
1265 	platform_set_drvdata(dev, nmk_chip);  in nmk_gpio_probe()
1272 	ret = gpiochip_irqchip_add(&nmk_chip->chip,  in nmk_gpio_probe()
1279 		gpiochip_remove(&nmk_chip->chip);  in nmk_gpio_probe()
1283 	gpiochip_set_chained_irqchip(&nmk_chip->chip,  in nmk_gpio_probe()
1285 				     nmk_chip->parent_irq,  in nmk_gpio_probe()
1287 	if (nmk_chip->latent_parent_irq > 0)  in nmk_gpio_probe()
1288 		gpiochip_set_chained_irqchip(&nmk_chip->chip,  in nmk_gpio_probe()
1290 					     nmk_chip->latent_parent_irq,  in nmk_gpio_probe()
1293 	dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);  in nmk_gpio_probe()
1698 		struct nmk_gpio_chip *nmk_chip;  in nmk_pmx_set()  local
1715 		nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);  in nmk_pmx_set()
1718 		clk_enable(nmk_chip->clk);  in nmk_pmx_set()
1727 		nmk_gpio_disable_lazy_irq(nmk_chip, bit);  in nmk_pmx_set()
1729 		__nmk_gpio_set_mode_safe(nmk_chip, bit,  in nmk_pmx_set()
1731 		clk_disable(nmk_chip->clk);  in nmk_pmx_set()
1763 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_request_enable()  local
1776 	nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);  in nmk_gpio_request_enable()
1780 	clk_enable(nmk_chip->clk);  in nmk_gpio_request_enable()
1783 	__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);  in nmk_gpio_request_enable()
1784 	clk_disable(nmk_chip->clk);  in nmk_gpio_request_enable()
1829 	struct nmk_gpio_chip *nmk_chip;  in nmk_pin_config_set()  local
1848 	nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);  in nmk_pin_config_set()
1884 			dev_dbg(nmk_chip->chip.dev,  in nmk_pin_config_set()
1893 		dev_dbg(nmk_chip->chip.dev,  in nmk_pin_config_set()
1900 		clk_enable(nmk_chip->clk);  in nmk_pin_config_set()
1904 			__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);  in nmk_pin_config_set()
1906 			__nmk_gpio_make_output(nmk_chip, bit, val);  in nmk_pin_config_set()
1908 			__nmk_gpio_make_input(nmk_chip, bit);  in nmk_pin_config_set()
1909 			__nmk_gpio_set_pull(nmk_chip, bit, pull);  in nmk_pin_config_set()
1912 		__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);  in nmk_pin_config_set()
1914 		__nmk_gpio_set_slpm(nmk_chip, bit, slpm);  in nmk_pin_config_set()
1915 		clk_disable(nmk_chip->clk);  in nmk_pin_config_set()